Abstract: Methods and devices are described herein for random cut patterning. A first metal line and a second metal line are formed within a cell of a substrate and extend in a vertical direction. A third metal line and a fourth metal line are formed within the cell and are perpendicular to the first metal line and the second metal line, respectively. A first circular region at one end of the first metal line is formed using a first patterning technique and a second circular region at one end of the second metal line is formed using a second patterning technique. The first circular region is laterally extended using a second patterning technique to form the third metal line and the second circular region is laterally extended using the second patterning technique to form the fourth metal line.

Abstract: An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.

Abstract: A method of generating an integrated circuit (IC) layout diagram includes arranging first conductive feature layout patterns in a cell region. The first conductive feature layout patterns extend in a first direction, and the cell region has opposite first and second cell boundaries extending in a second direction. Second conductive feature layout patterns are arranged in the cell region and extending in the first direction. The first and second conductive feature layout patterns are alternately arranged. First cut feature layout patterns are arranged on the first cell boundary of the cell region and on ends of the first conductive feature layout patterns. One of the first cut feature layout patterns is offset from another one of the first cut feature layout patterns in the first direction. The IC layout diagram including the first and second conductive feature layout patterns and the first cut feature layout patterns is generated.

Abstract: A system that generates a layout diagram has a processor that implements a method, the method including: generating first and second conductor shapes; generating first, second and third cap shapes correspondingly over the first and second conductor shapes; arranging a corresponding one of the second conductor shapes to be interspersed between each pair of neighboring ones of the first conductor shapes; generating first cut patterns over selected portions of corresponding ones of the first cap shapes; and generating second cut patterns over selected portions of corresponding ones of the second cap shapes. In some circumstances, the first cut patterns are designated as selective for a first etch sensitivity corresponding to the first cap shapes; and the second cut patterns are designated as selective for a second etch sensitivity corresponding to the second cap shapes.

Abstract: A heat dissipating assembly, adapted to be disposed at an M.2 expansion card and configured onto a main board with the M.2 expansion card, is provided. The heat dissipating assembly includes a first heat dissipating member and a first double-end screwing member. The first heat dissipating member is adapted to be disposed on the main board, located between the main board and the M.2 expansion card, and has at least one first through hole. The first double-end screwing member includes a first thread and a first nut having a first screw hole. The first thread passes through one of the at least one first through hole of the first heat dissipating member and is detachably fixed to the main board. The first nut presses against the first heat dissipating member.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a substrate. The first layer has a trench. The method includes forming a first spacer and a second spacer respectively over opposite inner walls of the trench. The first spacer and the second spacer are spaced apart from each other. The method includes removing a first portion of the first spacer to form a first gap in the first spacer, wherein a first part and a second part of the first spacer are spaced apart by the first gap, and the first gap communicates with the trench. The method includes forming a filling layer into the trench and the first gap to cover the first spacer and the second spacer. The filling layer, the first spacer, and the second spacer together form a strip structure. The method includes removing the first layer.

Abstract: A floated-type shielding mechanism including a cover, a shielding sheet, and a flexible conductor is provided. The cover is adapted to be fixed to a circuit board and covers a plurality of input/output (IO) ports of the circuit board. The shielding sheet is movably disposed at the cover and a back plate, and has a plurality of openings respectively corresponding to the IO ports. The flexible conductor deformably protrudes from an inner surface of the shielding sheet and is adapted to contact the IO ports. When the circuit board, the back plate, and the floated-type shielding mechanism are assembled into a case, the IO ports are exposed from a case opening and the flexible conductor is adapted to be deformed by pressing so that the shielding sheet presses against an inner wall surface around the case opening.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first conductive interconnect wire extending in a first direction over a substrate. A second conductive interconnect wire is arranged over the first conductive interconnect wire. A via rail is configured to electrically couple the first conductive interconnect wire and the second conductive interconnect wire. The first conductive interconnect wire and the second conductive interconnect wire extend as continuous structures past one or more sides of the via rail.

Abstract: A semiconductor device includes a buried metal line disposed in a semiconductor substrate, a first dielectric material on a first sidewall of the buried metal line and a second dielectric material on a second sidewall of the buried metal line, a first multiple fins disposed proximate the first sidewall of the buried metal line, a second multiple fins disposed proximate the second sidewall of the buried metal line, a first metal gate structure over the first multiple fins and over the buried metal line, wherein the first metal gate structure extends through the first dielectric material to contact the buried metal line, and a second metal gate structure over the second multiple fins and over the buried metal line.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a plurality of gate structures over a substrate, and forming a plurality of source and drain regions along opposing sides of the plurality of gate structures. A plurality of middle-of-the-line (MOL) structures are formed at locations laterally interleaved between the plurality of gate structures. The plurality of MOL structures are redefined by getting rid of a part but not all of one or more of the plurality of MOL structures. Redefining the plurality of MOL structures results in a plurality of MOL active structures arranged over the plurality of source and drain regions at an irregular pitch.

Abstract: The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature. A portion of the first feature extends over the spacer feature. The method further includes steps of removing the portion of the first feature extending over the spacer feature and removing the spacer feature. Other methods and associated patterned semiconductor wafers are also provided herein.

Abstract: A method of manufacturing a semiconductor device includes depositing a first material on a substrate, depositing on the substrate a second material that has an etch selectivity different from an etch selectively of the first material, depositing a spacer material on the first and second material, and etching the substrate using the spacer material as an etch mask to form a fin under the first material and a fin under the second material.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a plurality of gate structures extending in a first direction over a substrate between a plurality of source/drain regions. A lower power rail is formed extending in a second direction perpendicular to the first direction. A first connection pin is formed to be electrically coupled to one of the plurality of source/drain regions and to the lower power rail. The first connection pin is formed according to a cut mask having cut regions that define opposing ends of the first connection pin. An upper power rail is formed directly over the lower power rail and extending in the second direction. The upper power rail is electrically coupled to the first connection pin.

Abstract: Methods and devices are described herein for random cut patterning. A first metal line and a second metal line are formed within a cell of a substrate and extend in a vertical direction. A third metal line and a fourth metal line are formed within the cell and are perpendicular to the first metal line and the second metal line, respectively. A first circular region at one end of the first metal line is formed using a first patterning technique and a second circular region at one end of the second metal line is formed using a second patterning technique. The first circular region is laterally extended using a second patterning technique to form the third metal line and the second circular region is laterally extended using the second patterning technique to form the fourth metal line.

Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.

Abstract: The present disclosure describes a method for forming metal interconnects in an integrated circuit (IC). The method includes placing a metal interconnect in a layout area, determining a location of a redundant portion of the metal interconnect, and reducing, at the location, the length of the metal interconnect by a length of the redundant portion to form one or more active portions of the metal interconnect. The length of the redundant portion is a function of a distance between adjacent gate structures of the IC. The method further includes forming the one or more active portions on an interlayer dielectric (ILD) layer of the IC and forming vias on the one or more active portions, wherein the vias are positioned about 3 nm to about 5 nm away from an end of the one or more active portions.

Abstract: An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.

Abstract: In accordance with an aspect of the present disclosure, in a pattern forming method for a semiconductor device, a first opening is formed in an underlying layer disposed over a substrate. The first opening is expanded in a first axis by directional etching to form a first groove in the underlying layer. A resist pattern is formed over the underlying layer. The resist pattern includes a second opening only partially overlapping the first groove. The underlying layer is patterned by using the resist pattern as an etching mask to form a second groove.

Abstract: A method of defining a pattern-includes forming a plurality of cut shapes and a first plurality of openings within a first layer of a multi-layer hard mask to expose first portions of the second layer. A plurality of etch stops is formed by implanting an etch rate modifying species in a portion of the plurality of cut shapes. The first layer is directionally etched at the plurality of cut shapes such that the plurality of etch stops remain. A spacer layer is formed on the first layer and the first portions. A second plurality of openings is formed within the spacer layer to expose second portions of the second layer. The spacer layer is directionally etched to remove the spacer layer from sidewalls of the plurality of etch stops. Portions of the second layer exposed through the first plurality of openings and the second plurality of openings are etched.

Abstract: An IC layout diagram generation system includes a processor and a storage medium including computer program code configured to place a cell in an IC layout diagram, route a second metal segment to the cell by positioning the second metal segment along a first plurality of tracks having a first pitch in a first direction, route a third metal segment to the second metal segment by positioning the third metal segment along a second plurality of tracks having a second pitch in a second direction perpendicular to the first direction, and route a fourth metal segment to the third metal segment by positioning the fourth metal segment along a third plurality of tracks having a third pitch in the first direction, the third pitch being smaller than the second pitch. An IC layout file is generated based on the cell and the second, third, and fourth metal segments.