Abstract: A four signal line unit cell is formed on a substrate using a combination of an extreme ultraviolet photolithography process and one or more self aligned deposition processes. The photolithography process and the self aligned deposition processes result in spacers on a hard mask above the substrate. The spacers define a pattern of signal lines to be formed on the substrate for a unit cell. The photolithography process and self aligned deposition processes result in signal lines having a critical dimension much smaller than features that can be defined by the extreme ultraviolet photolithography process.

Abstract: A method for manufacturing a lithographic mask for an integrated circuit includes performing an optical proximity correction (OPC) process to an integrated circuit mask layout to produce a corrected mask layout. The method further includes performing an inverse lithographic technology (ILT) process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout. The method also includes performing an inverse lithographic technology (ILT) process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a plurality of gate structures arranged over a substrate and between adjacent ones of a plurality of source/drain regions within the substrate. A plurality of conductive contacts are electrically coupled to the plurality of source/drain regions. A first interconnect wire is arranged over the plurality of conductive contacts, and a second interconnect wire arranged over the first interconnect wire. A via rail contacts the first interconnect wire and the second interconnect wire. The via rail has an outer sidewall that faces an outermost edge of the plurality of source/drain regions and that is laterally separated from the outermost edge of the plurality of source/drain regions by a non-zero distance. The outer sidewall of the via rail continuously extends past two or more of the plurality of gate structures.

Abstract: An integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on said first dielectric layer, and a via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via.

Abstract: The disclosure relates to a cable concentrator and an electronic device having the same, where the cable concentrator includes main body and ground partition plate. The main body includes sidewall portions and bottom plate portion together forming accommodation portion to accommodate cable connectors. The bottom plate portion has positive terminal holes and negative terminal holes. The ground partition plate is located in the accommodation portion and divides the accommodation portion. The ground partition plate has ground bent tabs respectively corresponding to the negative terminal holes of the bottom plate portion and are electrically connected to negative terminals on a circuit board and thus grounding the negative terminals.

Abstract: A method of manufacturing a semiconductor device including the operations of defining a first metal pattern (MX-1) having a first metal pattern pitch (MX-1P); depositing an insulating layer over the first metal pattern; defining a core grid having a plurality of core locations having a coreX pitch (CoreXP) on the insulating layer; removing predetermined portions of the insulating layer to form a plurality of core openings through a predetermined set of the core locations; and elongating the core openings using a directional etch (DrE) to form expanded core openings that are used to form the next metal layer MX pattern.

Abstract: A device includes a first cell, a second cell, and first isolation portions. The second cell is adjacent the first cell. The first and second cells are arranged in a first direction, and the first cell includes first and second conductive structures. The first conductive structures extend in the first direction. Each of the first conductive structures has a first end facing the second cell. The second conductive structures extend in the first direction. The first and second conductive structures are alternately arranged in a second direction different from the first direction. The first isolation portions are respectively abutting the first ends of the first conductive structures. Two of the first isolation portions are misaligned with each other in the second direction.

Abstract: An integrated circuit includes a first and a second active region, a first contact, a second contact and a first insulating layer. The first active region is in a substrate, extends in a first direction, and is located on a first level. The second active region is in the substrate, extends in the first direction, is located on the first level, and is separated from the first active region in a second direction. The first contact is coupled to the first and the second active region, extends in the second direction, is located on a second level, and overlaps the first and the second active region. The second contact extends in the second direction, overlaps the first contact, and is located on a third level. The first insulating layer extends in the second direction, and is between the second contact and the first contact.

Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.

Abstract: In accordance with an aspect of the present disclosure, in a pattern forming method for a semiconductor device, a first opening is formed in an underlying layer disposed over a substrate. The first opening is expanded in a first axis by directional etching to form a first groove in the underlying layer. A resist pattern is formed over the underlying layer. The resist pattern includes a second opening only partially overlapping the first groove. The underlying layer is patterned by using the resist pattern as an etching mask to form a second groove.

Abstract: A casing assembly having at least one configuration for blocking extraneous material and including first shell part and second shell part. First shell part includes contact portion and first recess portion. Second shell part includes step portion and protrusion portion. Step portion is in contact with contact portion of first shell part and forms decorative slot exposed to outside with contact portion. First recess portion is located on side of contact portion that is located away from decorative slot. Protrusion portion is located on side of step portion that is located away from decorative slot and located in first recess portion. Protrusion portion has top surface facing toward first recess portion, first recess portion has bottom surface, and idle cavity is formed between top surface of protrusion portion and bottom surface of first recess portion.

Abstract: Methods of forming line-end extensions and devices having line-end extensions are provided. In some embodiments, a method includes forming a patterned photoresist on a first region of a hard mask layer. A line-end extension region is formed in the hard mask layer. The line-end extension region extends laterally outward from an end of the first region of the hard mask layer. The line-end extension region may be formed by changing a physical property of the hard mask layer at the line-end extension region.

Abstract: A heat dissipating assembly, adapted to be disposed at an M.2 expansion card and configured onto a main board with the M.2 expansion card, is provided. The heat dissipating assembly includes a first heat dissipating member and a first double-end screwing member. The first heat dissipating member is adapted to be disposed on the main board, located between the main board and the M.2 expansion card, and has at least one first through hole. The first double-end screwing member includes a first thread and a first nut having a first screw hole. The first thread passes through one of the at least one first through hole of the first heat dissipating member and is detachably fixed to the main board. The first nut presses against the first heat dissipating member.

Abstract: A wall mount assembly includes a case body, a latch member, a fixing plate, and a fixation member. A slit is formed on a rear surface of the case body. A first fixation hole is formed on an outer peripheral surface of the case body and communicates with the slit. The latch member is disposed on the rear surface. The fixing plate includes a latch hole and a lug. The latch member passes through the latch hole and engages with the fixing plate. The lug is inserted into the slit. When the latch member is located at a closed end of a sliding slot portion of the latch hole, a projection of the first fixation hole on the lug overlaps a second fixation hole of the lug. The fixation member is inserted into the first and the second fixation holes from the outer peripheral surface.

Abstract: A method for manufacturing a lithographic mask for an integrated circuit includes performing an optical proximity correction (OPC) process to an integrated circuit mask layout to produce a corrected mask layout. The method further includes performing an inverse lithographic technology (ILT) process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout. The method also includes performing an inverse lithographic technology (ILT) process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout.

Abstract: A method of defining a pattern includes forming a plurality of cut shapes and a first plurality of openings within a first layer of a multi-layer hard mask to expose first portions of the second layer. A plurality of etch stops is formed by implanting an etch rate modifying species in a portion of the plurality of cut shapes. The first layer is directionally etched at the plurality of cut shapes such that the plurality of etch stops remain. A spacer layer is formed on the first layer and the first portions. A second plurality of openings is formed within the spacer layer to expose second portions of the second layer. The spacer layer is directionally etched to remove the spacer layer from sidewalls of the plurality of etch stops. Portions of the second layer exposed through the first plurality of openings and the second plurality of openings are etched.

Abstract: An IC structure includes a first plurality of metal segments extending in a first metal layer in a first direction and having a first pitch in a second direction perpendicular to the first direction, a second plurality of metal segments extending in a second metal layer in the second direction and having a second pitch in the first direction, and a third plurality of metal segments extending in a third metal layer in the first direction and having a third pitch in the second direction. The second metal layer is a next consecutive layer overlying the first metal layer, the third metal layer is a next consecutive layer overlying the second metal layer, and a ratio of the second pitch to the third pitch is greater than one.

Abstract: A motherboard module is adapted for an M.2 expansion card to configure. The M.2 expansion card includes a connecting end and a fixing end. An edge of the fixing end has a semi-circular hole. The motherboard module includes a motherboard body, a locking member, and an abutting member. The motherboard body includes an expansion card slot, a first fixing hole, and a second fixing hole. The locking member is detachably fixed in the first fixing hole. The abutting member has a first end and a second end. The first end is detachably fixed in the second fixing hole. When the M.2 expansion card is installed on the motherboard module, the abutting member is located between the M.2 expansion card and the motherboard body, and the second end abuts against the M.2 expansion card. An electronic device is further provided.

Abstract: An integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on said first dielectric layer, and a via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via.

Abstract: The present disclosure relates to a method of forming an integrated chip. The method may be performed by forming first and second source regions within a substrate. The first and second source regions are separated by a drain region along a first direction. First and second middle-end-of-the-line (MEOL) structures are formed over the substrate. The first and second MEOL structures have bottom surfaces that continually extend past edges of the first and second source regions, respectively, along a second direction perpendicular to the first direction. A power rail is formed that is electrically coupled to the first and second MEOL structures. The power rail has a first interconnect wire, a via rail on and in contact with the first interconnect wire, and a second interconnect wire on and in contact with the via rail. The via rail continuously extends along the first direction past the first and second MEOL structures.