Abstract: A clamp ring including an inner periphery of increased diameter at locations where inwardly extending tabs are not located reduces the risk a workpiece that is placed in close proximity to the clamp ring or which contacts the clamp ring during processing will stick to the clamp ring.

Abstract: An apparatus for performing a deposition process on a semiconductor wafer includes a chamber, a wafer holder, and a shielding structure. The chamber contains a reaction area, the wafer holder is disposed in the chamber to hold the semiconductor wafer, and the reaction area is above the semiconductor wafer. The shielding structure is disposed in the chamber and isolates an inner sidewall of the chamber from the reaction area. The shielding structure includes a base member, a first member, and a second member. The base member is disposed between the inner sidewall of the chamber and the wafer holder. The first member is disposed on the base member and is windowless. The second member is disposed on the base member and within the first member, and the second member includes a sidewall provided with a first window to transfer the semiconductor wafer.

Abstract: A radio frequency apparatus includes a power amplifier circuit, a signal coupling circuit, an extraction circuit, and a harmonic filter circuit. The power amplifier circuit is configured to amplify a differential signal to output a to-be-filtered signal. The signal coupling circuit includes a primary side inductor and a secondary side inductor. The signal coupling circuit is configured to convert the to-be-filtered signal received by the primary side inductor into a single-ended signal outputted from the secondary side inductor. The extraction circuit has a center tap. The extraction circuit is configured to inductively couple to the primary side inductor and output a common mode signal from the center tap. The harmonic filter circuit is configured to perform a harmonic filtering on the single-ended signal according to the common mode signal, such that the secondary side inductor of the signal coupling circuit outputs a filtered signal.

Abstract: A power amplifying circuit includes a first input terminal applied with a first bias voltage, a first amplifying circuit generating a first output signal and a second output signal according to an input signal and a first matching circuit combining the first output signal and the second output signal to generate an output signal. The first amplifying circuit includes a first transistor having a first electrode coupled to the first input terminal and a second electrode applied with a second bias voltage and a second transistor having a first electrode s coupled to the first input terminal and a second electrode applied with a third bias voltage. The first transistor generates the first output signal according to the first bias voltage and the second bias voltage. The second transistor generates the second output signal according to the first bias voltage and the third bias voltage.

Abstract: The disclosure provides a method for correcting a 1 pulse per second (1PPS) signal and a timing receiver. In the embodiments of the disclosure, the proposed method allows the timing receiver to provide a corrected 1PPS signal with better quality to back-end slave devices, thereby ensuring that the synchronization effect of the slave devices is not overly affected by jitter in a single 1PPS signal.

Abstract: The present invention provides a method for fabricating patterned cellulose nanocrystal (CNC) composite nanofibers and thin films for optical and electromagnetic sensor and actuator application, comprising the following steps of: selecting materials for fabricating patterned cellulose nanocrystal (CNC) composite nanofibers; and fabricating patterned CNCs composite nanofibers by incorporating secondary phases either during electrospinning or post-processing, wherein the secondary phases may include dielectrics, electrically or magnetically activated nanoparticles or polymers and biological cells mechanically reinforced by CNCs.

Abstract: A critical dimension uniformity control method is provided. The method includes gathering a first CDU by a first critical dimension from a first wafer after being processed by a first surface process. The method includes determining a first calibration process based on the first CDU. The determining includes an intra dose correction step for correcting reticle-dependent deviation, a thru-slit dose sensitivity correction step for correcting time-dependent deviation, and an inter dose correction step for correcting process-dependent deviation. The method includes calibrating the first surface process by the first calibration process to determine a second surface process different from the first surface process.

Abstract: A system and method for cleaning a preclean process chamber in between wafer processing. The internal pressure of the preclean process chamber is reduced to a first pressure and a first gas that consists of oxygen and an inert or noble gas, is introduced into the chamber. Plasma is generated within the preclean process chamber using the first gas at the first pressure. Internal pressure is then reduced to a second pressure, less than the first, and the first gas is continued into the chamber. Plasma is then generated using the first gas at the second pressure. Thereafter, a second gas, consisting of an oxygen-free inert or noble gas, is introduced into the chamber at the second pressure, following which plasma is generated within the chamber using only the second gas.

Abstract: Methods of forming a semiconductor device structure are described. The method includes forming a first conductive feature including a conductive fill material over a substrate, forming an etch stop layer on the conductive fill material, forming an intermetallization dielectric on the etch stop layer, forming an opening in the etch stop layer and the intermetallization dielectric to expose a portion of the conductive fill material, forming a recess in the exposed portion of the conductive fill material, and the opening and the recess together form a rivet-shaped space. The method further includes forming a second conductive feature in the rivet-shaped space and forming a metal nitride layer over the intermetallization dielectric and the second conductive feature. The forming the metal nitride layer includes depositing the metal nitride layer and treating the metal nitride layer with a plasma treatment process.

Abstract: A foldable electronic device includes a first casing, a second casing, a hinge structure and a foldable display. The hinge structure connects the first casing and the second casing, and includes a plurality of supporting blocks, a plurality of first hinge blocks and a plurality of second hinge blocks. The supporting blocks are arranged side by side between the first casing and the second casing. The first hinge blocks and the second hinge blocks are respectively arranged at two sides of the supporting blocks. One of the first hinge blocks connects two of the supporting blocks adjacent to each other. One of the second hinge blocks connects two of the supporting blocks adjacent to each other. The foldable display includes a first bonding portion secured to the first casing, a second bonding portion secured to the second casing and a foldable portion aligned to the hinge structure.

Abstract: The invention discloses a dynamic random access memory (DRAM) device and a method of fabricating such DRAM device. The DRAM device according to the invention includes a plurality of bit lines formed on a semiconductor substrate, a plurality of first isolation stripes, a plurality of second isolation stripes, a plurality of transistors formed between the first isolation stripes and the second isolation stripes, a plurality of word lines, and a plurality of capacitors formed above the first isolation stripes and the second isolation stripes. The semiconductor substrate defines a longitudinal direction, a transverse direction, a normal direction, a plurality of columns in the longitudinal direction, and a plurality of rows in the transverse direction. The first isolation stripes and the second isolation stripes extend in the longitudinal direction. Each transistor corresponds to one of the columns and one of the rows.

Abstract: The present disclosure provides for an organic electroluminescent device (OLED) including an anode; a cathode; and an emissive layer, disposed between the anode and the cathode. The emissive layer includes a phosphorescent dopant, a first host, and a second host, wherein the first host transports holes, the second host transports electrons, and the first host is fully or partially deuterated. Consumer products that include the OLED are also provided.

Abstract: A mixture of carbazole and triazine derivatives that can be thermally evaporated from one crucible to fabricate thin films for electroluminescent devices is disclosed.

Abstract: A method includes etching a first portion and a second portion of a dummy gate stack to form a first opening and a second opening, respectively, and depositing a silicon nitride layer to fill the first opening and the second opening. The deposition of the silicon nitride layer comprises a first process selected from treating the silicon nitride layer using hydrogen radicals, implanting the silicon nitride layer, and combinations thereof. The method further includes etching a third portion of the dummy gate stack to form a trench, etching a semiconductor fin underlying the third portion to extend the trench down into a bulk portion of a semiconductor substrate underlying the dummy gate stack, and depositing a second silicon nitride layer into the trench.

Abstract: A semiconductor processing station includes first and second chambers, and a cooling stage. The second chamber includes a cooling pipe disposed inside the second chamber, and an external pipe. The cooling pipe includes a first segment disposed along a sidewall of the second chamber, and a second segment disposed perpendicular to the first segment and located above a wafer carrier in the second chamber. An end of the second segment is connected to an end of the first segment. The external pipe is connected to the second segment distal from the end of the second segment to provide a fluid to flow through the cooling pipe from an exterior to an interior of the second chamber. The fluid discharges toward the wafer carrier through the first segment. The first chamber is surrounded by the second chamber and the cooling stage, and communicates between the cooling stage and the second chamber.

Abstract: An electronic device may have a display with pixels configured to display an image. The pixels may be overlapped by a cover layer. An image transport layer may be formed from a coherent fiber bundle or Anderson localization material. The image transport layer may overlap the pixels and may have an input surface that receives the image from the pixels and a corresponding output surface on which the received image is viewable through the cover layer. Circuitry may be embedded within the image transport layer. The circuitry that is embedded within the image transport layer may include capacitive touch sensor circuitry, antenna resonating element structures, input-output components, signal lines, and other circuitry.

Abstract: A manufacturing method of a semiconductor package includes at least the following steps. A rear surface of a semiconductor die is attached to a patterned dielectric layer of a first redistribution structure through a die attach material, where a thickness of a portion of the die attach material filling a gap between the rear surface of the semiconductor die and a recessed area of the patterned dielectric layer is greater than a thickness of another portion of the die attach material interposed between the rear surface of the semiconductor die and a non-recessed area of the patterned dielectric layer. An insulating encapsulant is formed on the patterned dielectric layer of the first redistribution structure to cover the semiconductor die and the die attach material. Other methods for forming a semiconductor package are also provided.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first interconnect arranged within an inter-level dielectric (ILD) layer. The first interconnect has opposing sidewalls that are both laterally separated from closest neighboring interconnects within the ILD layer by one or more air-gaps along a cross-sectional view. A second interconnect is arranged within the ILD layer. The ILD layer laterally contacts opposing sidewalls of the second interconnect as viewed along the cross-sectional view.

Abstract: Provided is an OLED having an anode, a cathode and an organic emissive layer disposed between the anode and the cathode.

Abstract: A method includes etching a first portion and a second portion of a dummy gate stack to form a first opening and a second opening, respectively, and depositing a silicon nitride layer to fill the first opening and the second opening. The deposition of the silicon nitride layer comprises a first process selected from treating the silicon nitride layer using hydrogen radicals, implanting the silicon nitride layer, and combinations thereof. The method further includes etching a third portion of the dummy gate stack to form a trench, etching a semiconductor fin underlying the third portion to extend the trench down into a bulk portion of a semiconductor substrate underlying the dummy gate stack, and depositing a second silicon nitride layer into the trench.