Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a gate disposed on the substrate, a source disposed in the substrate and located on one side of the gate, a drain disposed in the substrate and located on another side of the gate, and a gate extending portion disposed on the substrate and located between the gate and the drain. The doping type of the gate is the opposite of that of the gate extending portion.

Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes a first semiconductor die, an insulating encapsulation laterally encapsulating the first semiconductor die, an electromagnetic shielding structure enclosing the first semiconductor die and a first portion of the insulating encapsulation, and a redistribution structure. The electromagnetic shielding structure includes a first conductive layer and a dielectric frame laterally covering the first conductive layer. The first conductive layer surrounds the first portion of the insulating encapsulation and extends to cover a first side of the first semiconductor die. The dielectric frame includes a first surface substantially leveled with the first conductive layer.

Abstract: A chip package including a first semiconductor die, conductive pillars, a dielectric structure, a second semiconductor die and insulating encapsulant is provided. The first semiconductor die includes a top surface having a first region and a second region. The conductive pillars are disposed over the second region of the first semiconductor die. The dielectric structure includes a first support portion disposed on the first region of the semiconductor die, and a second support portion physically separated from the first semiconductor die. The second semiconductor die is stacked over the first support portion and the second support portion, and is electrically connected to the first semiconductor die through the conductive pillars. The insulating encapsulant encapsulates the first semiconductor die, the second semiconductor die, the dielectric structure and the conductive pillars.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes a first semiconductor die, an insulating encapsulation laterally encapsulating the first semiconductor die, an electromagnetic shielding structure enclosing the first semiconductor die and a first portion of the insulating encapsulation, and a redistribution structure. The electromagnetic shielding structure includes a first conductive layer and a dielectric frame laterally covering the first conductive layer. The first conductive layer surrounds the first portion of the insulating encapsulation and extends to cover a first side of the first semiconductor die. The dielectric frame includes a first surface substantially leveled with the first conductive layer.

Abstract: A semiconductor package structure comprises a substrate, a die bonded to the substrate, and one or more stud bump structures connecting the die to the substrate, wherein each of the stud bump structures having a stud bump and a solder ball encapsulating the stud bump to enhance thermal dissipation and reduce high stress concentrations in the semiconductor package structure.

Abstract: Package structures and methods for forming the same are provided. The method includes forming a redistribution structure embedded in a passivation layer over a carrier substrate and bonding an integrated circuit die to the redistribution structure through first connectors. The method further includes removing the carrier substrate to expose a bottom portion of the redistribution structure and removing the bottom portion of the redistribution structure to form an opening in the passivation layer. The method further includes forming a second connector over the redistribution structure. In addition, the second connector includes an extending portion extending into the opening in the passivation layer.

Abstract: A manufacturing method of integrated fan-out package includes following steps. First and second dies are provided on adhesive layer formed on carrier. Heights of first and second dies are different. First and second dies respectively has first and second conductive posts each having substantially a same height. The dies are pressed against adhesive layer to make active surfaces thereof be in direct contact with adhesive layer and conductive posts thereof be submerged into adhesive layer. Adhesive layer is cured. Encapsulant is formed to encapsulate the dies. Carrier is removed from adhesive layer. Heights of first and second conductive posts are reduced and portions of the adhesive layer is removed. First and second conductive posts are laterally wrapped by and exposed from adhesive layer. Top surfaces of first and second conductive posts are leveled. Redistribution structure is formed over adhesive layer and is electrically connected to first and second conductive posts.

Abstract: An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first redistribution layer over and coupled to the first die, the first redistribution layer including one or more metal layers disposed in one or more dielectric layers, adhering a second die over the redistribution layer, laminating a first dielectric material over the second die and the first redistribution layer, forming first vias through the first dielectric material to the second die and forming second vias through the first dielectric material to the first redistribution layer, and forming a second redistribution layer over the first dielectric material and over and coupled to the first vias and the second vias.

Abstract: A method includes receiving a carrier with a plurality of wafers inside; supplying a purge gas to an inlet of the carrier; extracting an exhaust gas from an outlet of the carrier; and generating a health indicator of the carrier while performing the supplying of the purge gas and the extracting of the exhaust gas.

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

Abstract: The present invention features interferon-free therapies for the treatment of HCV. Preferably, the treatment is over a shorter duration of treatment, such as no more than 12 weeks. In one aspect, the treatment comprises administering at least two direct acting antiviral agents to a subject with HCV infection, wherein the treatment lasts for 12 weeks and does not include administration of either interferon or ribavirin, and said at least two direct acting antiviral agents comprise (a) Compound 1 or a pharmaceutically acceptable salt thereof and (b) Compound 2 or a pharmaceutically acceptable salt thereof.

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a protection layer encapsulating the semiconductor die. The chip package also includes a conductive structure in the protection layer and separated from the semiconductor die by the protection layer. The chip package further includes an interconnection structure over the conductive structure and the protection layer. The interconnection structure has a protruding portion between the conductive structure and the semiconductor die, and the protruding portion extends into the protection layer.

Abstract: Packaging methods for semiconductor devices are disclosed. A method of packaging a semiconductor device includes providing a workpiece including a plurality of packaging substrates. A portion of the workpiece is removed between the plurality of packaging substrates. A die is attached to each of the plurality of packaging substrates.

Abstract: A method comprises forming a plurality of interconnect structures including a dielectric layer, a metal line and a redistribution line over a carrier, attaching a semiconductor die on a first side of the plurality of interconnect structures, forming an underfill layer between the semiconductor die and the plurality of interconnect structures, mounting a top package on the first side the plurality of interconnect structures, wherein the top package comprises a plurality of conductive bumps, forming an encapsulation layer over the first side of the plurality of interconnect structures, wherein the top package is embedded in the encapsulation layer, detaching the carrier from the plurality of interconnect structures and mounting a plurality of bumps on a second side of the plurality of interconnect structures.

Abstract: A molding apparatus is configured for molding a semiconductor device and includes a lower mold and an upper mold. The lower mold is configured to carry the semiconductor device. The upper mold is disposed above the lower mold for receiving the semiconductor device and includes a mold part and a dynamic part. The mold part is configured to cover the upper surface of the semiconductor device. The dynamic part is disposed around a device receiving region of the upper mold and configured to move relatively to the mold part. A molding method and a molded semiconductor device are also provided.

Abstract: A package structure including a semiconductor die, a warpage control layer, an insulating encapsulant and a redistribution layer is provided. The semiconductor die has an active surface and a backside surface opposite to the active surface. The warpage control layer is disposed on the backside surface of the semiconductor die, wherein the warpage control layer comprises a material having a Young's Modulus of 100 GPa or more. The insulating encapsulant is encapsulating the semiconductor die and the warpage control layer. The redistribution layer is located on the insulating encapsulant and over the active surface of the semiconductor die.

Abstract: The present invention features interferon-free therapies for the treatment of HCV. Preferably, the treatment is over a shorter duration of treatment, such as no more than 12 weeks. In one aspect, the treatment comprises administering at least two direct acting antiviral agents to a subject with HCV infection, wherein the treatment lasts for 12 weeks and does not include administration of either interferon or ribavirin, and said at least two direct acting antiviral agents comprise (a) Compound 1 or a pharmaceutically acceptable salt thereof and (b) Compound 2 or a pharmaceutically acceptable salt thereof.

Abstract: A method embodiment includes forming a sacrificial film layer over a top surface of a die, the die having a contact pad at the top surface. The die is attached to a carrier, and a molding compound is formed over the die and the sacrificial film layer. The molding compound extends along sidewalls of the die. The sacrificial film layer is exposed. The contact pad is exposed by removing at least a portion of the sacrificial film layer. A first polymer layer is formed over the die, and a redistribution layer (RDL) is formed over the die and electrically connects to the contact pad.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and a light-collimating layer. The substrate has a plurality of pixels. The light-collimating layer is disposed on the substrate, and the light-collimating layer includes a transparent material layer, a first light-shielding layer, a second light-shielding layer and a plurality of transparent pillars. The transparent material layer covers the pixels. The first light-shielding layer is disposed on the substrate and the first light-shielding layer has a plurality of holes corresponding to the pixels. The second light-shielding layer is disposed on the first light-shielding layer. The transparent pillars are disposed in the second light-shielding layer.