TECHNICAL FIELD The technical field relates to a semiconductor structure capable of reducing drain-to-gate capacitance.
BACKGROUND In many semiconductor structures, a field plate structure disposed between the gate and the drain is often used as an important component for dispersing the electric field strength of the drain region (the drift region) to avoid damage of components caused by excessive concentration of the electric field near the drain region (the drift region). However, when the field plate structure is electrically connected to its adjacent gate, the field plate structure simultaneously contributes a considerable degree of the drain-to-gate capacitance.
In general, with high-speed switching components that are expected to achieve high-performance electric power conversion, it is necessary to minimize power loss during operation to maintain high-speed conversion between components. However, when the switch is turned on and there is a large current flowing, if the above-mentioned drain-to-gate capacitance exists in the transistor adjacent to the phase, an unwanted current will flow through this transistor due to the coupling effect, resulting in power loss of the switching component.
At present, there are several ways to reduce the drain-to-gate capacitance, such as electrically connecting the field plate structure and the source, or increasing the thickness of the oxide layer underneath the field plate or the gate. Alternatively, a dopant having an opposite doping type to the drain region (the drift region) is implanted on the surface of the substrate underneath the gate. However, the various methods described above still have many disadvantages, such as an increase in resistance.
Therefore, development of a semiconductor structure capable of dispersing the electric field strength of a drain region (a drift region) and reducing the drain-to-gate capacitance is desirable.
SUMMARY In accordance with one embodiment of the invention, a semiconductor structure is provided. The semiconductor structure includes a substrate, a gate disposed on the substrate, a source disposed in the substrate and located on one side of the gate, a drain disposed in the substrate and located on another side of the gate, and a gate extending portion disposed on the substrate and located between the gate and the drain. The doping type of the gate is the opposite of that of the gate extending portion.
In some embodiments, the substrate is a P-type substrate or an N-type substrate. In some embodiments, when the substrate is a P-type substrate, the doping type of the gate is N type, the doping type of the source is N type, the doping type of the drain is N type, and the doping type of the gate extending portion is P type. In some embodiments, when the substrate is an N-type substrate, the doping type of the gate is P type, the doping type of the source is P type, the doping type of the drain is P type, and the doping type of the gate extending portion is N type. In some embodiments, the gate and the gate extending portion include polysilicon doped with P-type dopants or polysilicon doped with N-type dopants.
In some embodiments, the gate is substantially in contact with the gate extending portion. In some embodiments, the gate is substantially separated from the gate extending portion.
In some embodiments, when the gate is substantially in contact with the gate extending portion, the semiconductor structure further includes a metal field plate disposed on the substrate and located between the gate extending portion and the drain. In some embodiments, the semiconductor structure further includes an oxide layer disposed on the substrate and underneath the metal field plate. In some embodiments, the metal field plate is electrically connected with the gate and the gate extending portion. In some embodiments, the metal field plate is electrically connected with the source. In some embodiments, the width ratio of the gate extending portion and the gate is in a range from about 0.3 to about 1.2. In some embodiments, the sum of the width of the gate extending portion and the width of the gate is a fixed value.
In some embodiments, when the gate is substantially separated from the gate extending portion, the gate is electrically connected with the gate extending portion. In some embodiments, the gate extending portion is electrically connected with the source.
In the present invention, two regions with opposite doping types (for example, the region adjacent to the drain is P-type doped (defined as the gate extending portion), and the region away from the drain is N-type doped (defined as the gate)) are formed in the polysilicon gate of a MOS transistor using implantation processes. Due to the effect of capacitor series connection, the drain-to-gate capacitance is reduced. As the ratio of the width of the gate extending portion and the width of the gate increases, the drain-to-gate capacitance decreases more obviously. At this time, the gate extending portion has the function of field plate, which can effectively disperse the electric field strength of the drain region (the drift region) and prevent the component from being damaged in a high-voltage operation environment. In addition, the two regions having opposite doping types can be fabricated into two separated structures. On the one hand, the gate extending portion can have the function of field plate, and on the other hand, the effect of reducing the drain-to-gate capacitance can be achieved. The cost of the present invention is low, and it is easily fabricated without changing the existing MOS process specifications. Due to the dropping in the drain-to-gate capacitance, undesired current flow caused by the coupling effect of the transistor is avoided. The specific semiconductor structure design of the present invention can effectively reduce the power loss of the switching components, greatly improving the switching frequency and achieving high-efficiency electric power conversion.
A detailed description is given in the following embodiments with reference to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
FIG. 1 is a cross-sectional view of a semiconductor structure in accordance with one embodiment of the invention;
FIG. 2 is a cross-sectional view of a semiconductor structure in accordance with one embodiment of the invention;
FIG. 3 is a cross-sectional view of a semiconductor structure in accordance with one embodiment of the invention;
FIG. 4 is a cross-sectional view of a semiconductor structure in accordance with one embodiment of the invention;
FIG. 5 is a cross-sectional view of a semiconductor structure in accordance with one embodiment of the invention;
FIG. 6 is a cross-sectional view of a semiconductor structure in accordance with one embodiment of the invention; and
FIG. 7 is a cross-sectional view of a semiconductor structure in accordance with one embodiment of the invention.
DETAILED DESCRIPTION The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
Referring to FIG. 1, in accordance with one embodiment of the invention, a semiconductor structure 10 is provided. FIG. 1 is a cross-sectional view of the semiconductor structure 10.
As shown in FIG. 1, the semiconductor structure 10 includes a substrate 12, a gate 14, a source 16, a drain 18, a gate extending portion 20 and a drain drift region 22. The gate 14 is disposed on the substrate 12. The source 16 is disposed in the substrate 12 and located on one side of the gate 14. The drain 18 is disposed in the substrate 12 and located on another side of the gate 14. The gate extending portion 20 is disposed on the substrate 12 and located between the gate 14 and the drain 18. The drain drift region 22 is formed in the substrate 12 and surrounds the drain 18. Specifically, the doping type of the gate 14 is the opposite of that of the gate extending portion 20. For example, when the doping type of the gate 14 is N type, the doping type of the gate extending portion 20 is P type, or when the doping type of the gate 14 is P type, the doping type of the gate extending portion 20 is N type. Since the doping type of the gate 14 is the opposite of the doping type of the gate extending portion 20, a depletion region (not shown) is naturally formed between the gate 14 and the gate extending portion 20.
In some embodiments, the substrate 12 is a P-type semiconductor substrate or an N-type semiconductor substrate. In some embodiments, when the substrate 12 is a P-type semiconductor substrate, the doping type of the gate 14 is N type, the doping type of the source 16 is N type, the doping type of the drain 18 is N type, and the doping type of the gate extending portion 20 is P type. In some embodiments, when the substrate 12 is an N-type semiconductor substrate, the doping type of the gate 14 is P type, the doping type of the source 16 is P type, the doping type of the drain 18 is P type, and the doping type of the gate extending portion 20 is N type. In some embodiments, the gate 14 and the gate extending portion 20 include polysilicon doped with P-type dopants or polysilicon doped with N-type dopants.
In FIG. 1, the gate 14 is substantially in contact with the gate extending portion 20. For example, the gate 14 is substantially in contact laterally with the gate extending portion 20 (i.e. the sidewall of the gate 14 is substantially in contact with the sidewall of the gate extending portion 20). In some embodiments, the ratio of the width “WE” of the gate extending portion 20 and the width “WG” of the gate 14 is in a range from about 0.3 to about 1.2. For example, the width “WE” of the gate extending portion 20 is about 0.15 μm, and the width “WG” of the gate 14 is about 0.5 μm (the ratio thereof is about 0.3), or the width “WE” of the gate extending portion 20 is about 0.25 μm, and the width “WG” of the gate 14 is about 0.4 μm (the ratio thereof is about 0.625), or the width “WE” of the gate extending portion 20 is about 0.35 μm, and the width “WG” of the gate 14 is about 0.3 m (the ratio thereof is about 1.17). In some embodiments, the ratio of the width “WE” of the gate extending portion 20 and the width “WG” of the gate 14 may also be other suitable ranges, and is not limited thereto. In some embodiments, the boundary “BE” of the gate extending portion 20 and the gate 14 is not more than the range of the drain drift region 22 (i.e. the gate extending portion 20 only overlaps the drain drift region 22 in the substrate 12). In some embodiments, in the semiconductor structure 10, the sum “WT” of the width “WE” of the gate extending portion 20 and the width “WG” of the gate 14 is a fixed value. For example, when the ratio of the width “WE” of the gate extending portion 20 and the width “WG” of the gate 14 is in a range from about 0.3 to about 1.2, the sum “WT” of the width “WE” of the gate extending portion 20 and the width “WG” of the gate 14 is about 0.65 μm (For example, the width “WE” of the gate extending portion 20 is about 0.15 μm, and the width “WG” of the gate 14 is about 0.5 μm, or the width “WE” of the gate extending portion 20 is about 0.25 μm, and the width “WG” of the gate 14 is about 0.4 μm, or the width “WE” of the gate extending portion 20 is about 0.35 μm, and the width “WG” of the gate 14 is about 0.3 μm). In some embodiments, according to different product requirements, the sum “WT” of the width “WE” of the gate extending portion 20 and the width “WG” of the gate 14 may also include other suitable sizes, and is not limited thereto.
In FIG. 1, the semiconductor structure 10 further includes a metal field plate 24 disposed on the substrate 12 and located between the gate extending portion 20 and the drain 18. As shown in FIG. 1, the semiconductor structure 10 further includes an oxide layer 26 disposed on the substrate 12 and underneath the metal field plate 24. In FIG. 1, the metal field plate 24 and the underlying oxide layer 26 cover a portion of the gate extending portion 20. The metal field plate 24 is electrically connected with the gate 14 and the gate extending portion 20 by the metal layer 28. Since the metal field plate 24 is electrically connected with the gate extending portion 20, in the present embodiment, the gate extending portion 20 can also be regarded as another part of the metal field plate. In some embodiments, the fabrication method of the gate 14 and the gate extending portion 20 which are substantially in contact with each other is shown. For example, first, a patterned polysilicon layer is formed on the substrate 12. Next, an N-type implantation process is performed on a region of the patterned polysilicon layer in which the gate 14 is predetermined to be formed, and a P-type implantation process is performed on a region of the patterned polysilicon layer in which the gate extending portion 20 is predetermined to be formed. Optionally, a P-type implantation process is performed on a region of the patterned polysilicon layer in which the gate 14 is predetermined to be formed, and an N-type implantation process is performed on a region of the patterned polysilicon layer in which the gate extending portion 20 is predetermined to be formed. So far, the fabrication of the gate 14 and the gate extending portion 20 having opposite doping types and substantially in contact with each other is completed.
Referring to FIG. 2, in accordance with one embodiment of the invention, a semiconductor structure 10 is provided. FIG. 2 is a cross-sectional view of the semiconductor structure 10.
As shown in FIG. 2, the semiconductor structure 10 includes a substrate 12, a gate 14, a source 16, a drain 18, a gate extending portion 20 and a drain drift region 22. The gate 14 is disposed on the substrate 12. The source 16 is disposed in the substrate 12 and located on one side of the gate 14. The drain 18 is disposed in the substrate 12 and located on another side of the gate 14. The gate extending portion 20 is disposed on the substrate 12 and located between the gate 14 and the drain 18. The drain drift region 22 is formed in the substrate 12 and surrounds the drain 18. Specifically, the doping type of the gate 14 is the opposite of that of the gate extending portion 20. For example, when the doping type of the gate 14 is N type, the doping type of the gate extending portion 20 is P type, or when the doping type of the gate 14 is P type, the doping type of the gate extending portion 20 is N type. Since the doping type of the gate 14 is the opposite of the doping type of the gate extending portion 20, a depletion region (not shown) is naturally formed between the gate 14 and the gate extending portion 20.
In some embodiments, the substrate 12 is a P-type semiconductor substrate or an N-type semiconductor substrate. In some embodiments, when the substrate 12 is a P-type semiconductor substrate, the doping type of the gate 14 is N type, the doping type of the source 16 is N type, the doping type of the drain 18 is N type, and the doping type of the gate extending portion 20 is P type. In some embodiments, when the substrate 12 is an N-type semiconductor substrate, the doping type of the gate 14 is P type, the doping type of the source 16 is P type, the doping type of the drain 18 is P type, and the doping type of the gate extending portion 20 is N type. In some embodiments, the gate 14 and the gate extending portion 20 include polysilicon doped with P-type dopants or polysilicon doped with N-type dopants.
In FIG. 2, the gate 14 is substantially in contact with the gate extending portion 20. For example, the gate 14 is substantially in contact laterally with the gate extending portion 20 (i.e. the sidewall of the gate 14 is substantially in contact with the sidewall of the gate extending portion 20). In some embodiments, the ratio of the width “WE” of the gate extending portion 20 and the width “WG” of the gate 14 is in a range from about 0.3 to about 1.2. For example, the width “WE” of the gate extending portion 20 is about 0.15 μm, and the width “WG” of the gate 14 is about 0.5 μm (the ratio thereof is about 0.3), or the width “WE” of the gate extending portion 20 is about 0.25 μm, and the width “WG” of the gate 14 is about 0.4 μm (the ratio thereof is about 0.625), or the width “WE” of the gate extending portion 20 is about 0.35 μm, and the width “WG” of the gate 14 is about 0.3 m (the ratio thereof is about 1.17). In some embodiments, the ratio of the width “WE” of the gate extending portion 20 and the width “WG” of the gate 14 may also be other suitable ranges, and is not limited thereto. In some embodiments, the boundary “BE” of the gate extending portion 20 and the gate 14 is not more than the range of the drain drift region 22 (i.e. the gate extending portion 20 only overlaps the drain drift region 22 in the substrate 12). In some embodiments, in the semiconductor structure 10, the sum “WT” of the width “WE” of the gate extending portion 20 and the width “WG” of the gate 14 is a fixed value. For example, when the ratio of the width “WE” of the gate extending portion 20 and the width “WG” of the gate 14 is in a range from about 0.3 to about 1.2, the sum “WT” of the width “WE” of the gate extending portion 20 and the width “WG” of the gate 14 is about 0.65 μm (For example, the width “WE” of the gate extending portion 20 is about 0.15 μm, and the width “WG” of the gate 14 is about 0.5 μm, or the width “WE” of the gate extending portion 20 is about 0.25 μm, and the width “WG” of the gate 14 is about 0.4 μm, or the width “WE” of the gate extending portion 20 is about 0.35 μm, and the width “WG” of the gate 14 is about 0.3 μm). In some embodiments, according to different product requirements, the sum “WT” of the width “WE” of the gate extending portion 20 and the width “WG” of the gate 14 may also include other suitable sizes, and is not limited thereto.
In FIG. 2, the semiconductor structure 10 further includes a metal field plate 24 disposed on the substrate 12 and located between the gate extending portion 20 and the drain 18. As shown in FIG. 2, the semiconductor structure 10 further includes an oxide layer 26 disposed on the substrate 12 and underneath the metal field plate 24. In FIG. 2, the metal field plate 24 and the underlying oxide layer 26 cover a portion of the gate extending portion 20. The metal field plate 24 is electrically connected with the source 16 by the metal layer 30. In some embodiments, the fabrication method of the gate 14 and the gate extending portion 20 which are substantially in contact with each other is shown. For example, first, a patterned polysilicon layer is formed on the substrate 12. Next, an N-type implantation process is performed on a region of the patterned polysilicon layer in which the gate 14 is predetermined to be formed, and a P-type implantation process is performed on a region of the patterned polysilicon layer in which the gate extending portion 20 is predetermined to be formed. Optionally, a P-type implantation process is performed on a region of the patterned polysilicon layer in which the gate 14 is predetermined to be formed, and an N-type implantation process is performed on a region of the patterned polysilicon layer in which the gate extending portion 20 is predetermined to be formed. So far, the fabrication of the gate 14 and the gate extending portion 20 having opposite doping types and substantially in contact with each other is completed.
Referring to FIG. 3, in accordance with one embodiment of the invention, a semiconductor structure 10 is provided. FIG. 3 is a cross-sectional view of the semiconductor structure 10.
As shown in FIG. 3, the semiconductor structure 10 includes a substrate 12, a gate 14, a source 16, a drain 18, a gate extending portion 20 and a drain drift region 22. The gate 14 is disposed on the substrate 12. The source 16 is disposed in the substrate 12 and located on one side of the gate 14. The drain 18 is disposed in the substrate 12 and located on another side of the gate 14. The gate extending portion 20 is disposed on the substrate 12 and located between the gate 14 and the drain 18. The drain drift region 22 is formed in the substrate 12 and surrounds the drain 18. Specifically, the doping type of the gate 14 is the opposite of that of the gate extending portion 20. For example, when the doping type of the gate 14 is N type, the doping type of the gate extending portion 20 is P type, or when the doping type of the gate 14 is P type, the doping type of the gate extending portion 20 is N type. Since the doping type of the gate 14 is the opposite of the doping type of the gate extending portion 20, a depletion region (not shown) is naturally formed between the gate 14 and the gate extending portion 20.
In some embodiments, the substrate 12 is a P-type semiconductor substrate or an N-type semiconductor substrate. In some embodiments, when the substrate 12 is a P-type semiconductor substrate, the doping type of the gate 14 is N type, the doping type of the source 16 is N type, the doping type of the drain 18 is N type, and the doping type of the gate extending portion 20 is P type. In some embodiments, when the substrate 12 is an N-type semiconductor substrate, the doping type of the gate 14 is P type, the doping type of the source 16 is P type, the doping type of the drain 18 is P type, and the doping type of the gate extending portion 20 is N type. In some embodiments, the gate 14 and the gate extending portion 20 include polysilicon doped with P-type dopants or polysilicon doped with N-type dopants.
In FIG. 3, the gate 14 is substantially in contact with the gate extending portion 20. For example, the gate 14 is substantially in contact laterally with the gate extending portion 20 (i.e. the sidewall of the gate 14 is substantially in contact with the sidewall of the gate extending portion 20). In the present embodiment, the ratio of the width “WE” of the gate extending portion 20 (P-type doping) and the width “WG” of the gate 14 (N-type doping) is about 0.3. In this situation, the width “WE” of the gate extending portion 20 is about 0.15 μm, and the width “WG” of the gate 14 is about 0.5 m. In some embodiments, the ratio of the width “WE” of the gate extending portion 20 and the width “WG” of the gate 14 may also be other suitable ranges, and is not limited thereto. In some embodiments, the boundary “BE” of the gate extending portion 20 and the gate 14 is not more than the range of the drain drift region 22 (i.e. the gate extending portion 20 only overlaps the drain drift region 22 in the substrate 12). In some embodiments, in the semiconductor structure 10, the sum “WT” of the width “WE” of the gate extending portion 20 and the width “WG” of the gate 14 is a fixed value. In the present embodiment, when the ratio of the width “WE” of the gate extending portion 20 and the width “WG” of the gate 14 is about 0.3, the sum “WT” of the width “WE” of the gate extending portion 20 and the width “WG” of the gate 14 is about 0.65 μm (that is, the width “WE” of the gate extending portion 20 is about 0.15 μm, and the width “WG” of the gate 14 is about 0.5 μm). In some embodiments, according to different product requirements, the sum “WT” of the width “WE” of the gate extending portion 20 and the width “WG” of the gate 14 may also include other suitable sizes, and is not limited thereto. In the present embodiment, the gate extending portion 20 can be considered a metal field plate. The component operation is performed with the semiconductor structure of the present embodiment. Various operating conditions (for example, threshold voltage (Vth), linear-region drain current (Idlin), saturation-region drain current (Idsat), static breakdown voltage (BVoff)), and the drain-to-gate capacitance (Cgd) are shown in Table 1.
In some embodiments, the fabrication method of the gate 14 and the gate extending portion 20 which are substantially in contact with each other is shown. For example, first, a patterned polysilicon layer is formed on the substrate 12. Next, an N-type implantation process is performed on a region (the width thereof is about 0.5 μm) of the patterned polysilicon layer in which the gate 14 is predetermined to be formed, and a P-type implantation process is performed on a region (the width thereof is about 0.15 μm) of the patterned polysilicon layer in which the gate extending portion 20 is predetermined to be formed (as the present embodiment). Optionally, a P-type implantation process is performed on a region (the width thereof is about 0.5 μm) of the patterned polysilicon layer in which the gate 14 is predetermined to be formed, and an N-type implantation process is performed on a region (the width thereof is about 0.15 μm) of the patterned polysilicon layer in which the gate extending portion 20 is predetermined to be formed. So far, the fabrication of the gate 14 and the gate extending portion 20 having opposite doping types and substantially in contact with each other is completed.
Referring to FIG. 4, in accordance with one embodiment of the invention, a semiconductor structure 10 is provided. FIG. 4 is a cross-sectional view of the semiconductor structure 10.
As shown in FIG. 4, the semiconductor structure 10 includes a substrate 12, a gate 14, a source 16, a drain 18, a gate extending portion 20 and a drain drift region 22. The gate 14 is disposed on the substrate 12. The source 16 is disposed in the substrate 12 and located on one side of the gate 14. The drain 18 is disposed in the substrate 12 and located on another side of the gate 14. The gate extending portion 20 is disposed on the substrate 12 and located between the gate 14 and the drain 18. The drain drift region 22 is formed in the substrate 12 and surrounds the drain 18. Specifically, the doping type of the gate 14 is the opposite of that of the gate extending portion 20. For example, when the doping type of the gate 14 is N type, the doping type of the gate extending portion 20 is P type, or when the doping type of the gate 14 is P type, the doping type of the gate extending portion 20 is N type. Since the doping type of the gate 14 is the opposite of the doping type of the gate extending portion 20, a depletion region (not shown) is naturally formed between the gate 14 and the gate extending portion 20.
In some embodiments, the substrate 12 is a P-type semiconductor substrate or an N-type semiconductor substrate. In some embodiments, when the substrate 12 is a P-type semiconductor substrate, the doping type of the gate 14 is N type, the doping type of the source 16 is N type, the doping type of the drain 18 is N type, and the doping type of the gate extending portion 20 is P type. In some embodiments, when the substrate 12 is an N-type semiconductor substrate, the doping type of the gate 14 is P type, the doping type of the source 16 is P type, the doping type of the drain 18 is P type, and the doping type of the gate extending portion 20 is N type. In some embodiments, the gate 14 and the gate extending portion 20 include polysilicon doped with P-type dopants or polysilicon doped with N-type dopants.
In FIG. 4, the gate 14 is substantially in contact laterally with the gate extending portion 20. For example, the gate 14 is substantially in contact with the gate extending portion 20 (i.e. the sidewall of the gate 14 is substantially in contact with the sidewall of the gate extending portion 20). In the present embodiment, the ratio of the width “WE” of the gate extending portion 20 (P-type doping) and the width “WG” of the gate 14 (N-type doping) is about 0.625. In this situation, the width “WE” of the gate extending portion 20 is about 0.25 μm, and the width “WG” of the gate 14 is about 0.4 m. In some embodiments, the ratio of the width “WE” of the gate extending portion 20 and the width “WG” of the gate 14 may also be other suitable ranges, and is not limited thereto. In some embodiments, the boundary “BE” of the gate extending portion 20 and the gate 14 is not more than the range of the drain drift region 22 (i.e. the gate extending portion 20 only overlaps the drain drift region 22 in the substrate 12). In some embodiments, in the semiconductor structure 10, the sum “WT” of the width “WE” of the gate extending portion 20 and the width “WG” of the gate 14 is a fixed value. In the present embodiment, when the ratio of the width “WE” of the gate extending portion 20 and the width “WG” of the gate 14 is about 0.625, the sum “WT” of the width “WE” of the gate extending portion 20 and the width “WG” of the gate 14 is about 0.65 μm (that is, the width “WE” of the gate extending portion 20 is about 0.25 μm, and the width “WG” of the gate 14 is about 0.4 μm). In some embodiments, according to different product requirements, the sum “WT” of the width “WE” of the gate extending portion 20 and the width “WG” of the gate 14 may also include other suitable sizes, and is not limited thereto. In the present embodiment, the gate extending portion 20 can be considered a metal field plate. The component operation is performed with the semiconductor structure of the present embodiment. Various operating conditions (for example, threshold voltage (Vth), linear-region drain current (Idlin), saturation-region drain current (Idsat), static breakdown voltage (BVoff)), and the drain-to-gate capacitance (Cgd) are shown in Table 1.
In some embodiments, the fabrication method of the gate 14 and the gate extending portion 20 which are substantially in contact with each other is shown. For example, first, a patterned polysilicon layer is formed on the substrate 12. Next, an N-type implantation process is performed on a region (the width thereof is about 0.4 μm) of the patterned polysilicon layer in which the gate 14 is predetermined to be formed, and a P-type implantation process is performed on a region (the width thereof is about 0.25 μm) of the patterned polysilicon layer in which the gate extending portion 20 is predetermined to be formed (as the present embodiment). Optionally, a P-type implantation process is performed on a region (the width thereof is about 0.4 μm) of the patterned polysilicon layer in which the gate 14 is predetermined to be formed, and an N-type implantation process is performed on a region (the width thereof is about 0.25 μm) of the patterned polysilicon layer in which the gate extending portion 20 is predetermined to be formed. So far, the fabrication of the gate 14 and the gate extending portion 20 having opposite doping types and substantially in contact with each other is completed.
Referring to FIG. 5, in accordance with one embodiment of the invention, a semiconductor structure 10 is provided. FIG. 5 is a cross-sectional view of the semiconductor structure 10.
As shown in FIG. 5, the semiconductor structure 10 includes a substrate 12, a gate 14, a source 16, a drain 18, a gate extending portion 20 and a drain drift region 22. The gate 14 is disposed on the substrate 12. The source 16 is disposed in the substrate 12 and located on one side of the gate 14. The drain 18 is disposed in the substrate 12 and located on another side of the gate 14. The gate extending portion 20 is disposed on the substrate 12 and located between the gate 14 and the drain 18. The drain drift region 22 is formed in the substrate 12 and surrounds the drain 18. Specifically, the doping type of the gate 14 is the opposite of that of the gate extending portion 20. For example, when the doping type of the gate 14 is N type, the doping type of the gate extending portion 20 is P type, or when the doping type of the gate 14 is P type, the doping type of the gate extending portion 20 is N type. Since the doping type of the gate 14 is the opposite of the doping type of the gate extending portion 20, a depletion region (not shown) is naturally formed between the gate 14 and the gate extending portion 20.
In some embodiments, the substrate 12 is a P-type semiconductor substrate or an N-type semiconductor substrate. In some embodiments, when the substrate 12 is a P-type semiconductor substrate, the doping type of the gate 14 is N type, the doping type of the source 16 is N type, the doping type of the drain 18 is N type, and the doping type of the gate extending portion 20 is P type. In some embodiments, when the substrate 12 is an N-type semiconductor substrate, the doping type of the gate 14 is P type, the doping type of the source 16 is P type, the doping type of the drain 18 is P type, and the doping type of the gate extending portion 20 is N type. In some embodiments, the gate 14 and the gate extending portion 20 include polysilicon doped with P-type dopants or polysilicon doped with N-type dopants.
In FIG. 5, the gate 14 is substantially in contact with the gate extending portion 20. For example, the gate 14 is substantially in contact laterally with the gate extending portion 20 (i.e. the sidewall of the gate 14 is substantially in contact with the sidewall of the gate extending portion 20). In the present embodiment, the ratio of the width “WE” of the gate extending portion 20 (P-type doping) and the width “WG” of the gate 14 (N-type doping) is about 1.17. In this situation, the width “WE” of the gate extending portion 20 is about 0.35 μm, and the width “WG” of the gate 14 is about 0.3 m. In some embodiments, the ratio of the width “WE” of the gate extending portion 20 and the width “WG” of the gate 14 may also be other suitable ranges, and is not limited thereto. In some embodiments, the boundary “BE” of the gate extending portion 20 and the gate 14 is not more than the range of the drain drift region 22 (i.e. the gate extending portion 20 only overlaps the drain drift region 22 in the substrate 12). In some embodiments, in the semiconductor structure 10, the sum “WT” of the width “WE” of the gate extending portion 20 and the width “WG” of the gate 14 is a fixed value. In the present embodiment, when the ratio of the width “WE” of the gate extending portion 20 and the width “WG” of the gate 14 is about 1.17, the sum “WT” of the width “WE” of the gate extending portion 20 and the width “WG” of the gate 14 is about 0.65 μm (that is, the width “WE” of the gate extending portion 20 is about 0.35 μm, and the width “WG” of the gate 14 is about 0.3 μm). In some embodiments, according to different product requirements, the sum “WT” of the width “WE” of the gate extending portion 20 and the width “WG” of the gate 14 may also include other suitable sizes, and is not limited thereto. In the present embodiment, the gate extending portion 20 can be considered a metal field plate. The component operation is performed with the semiconductor structure of the present embodiment. Various operating conditions (for example, threshold voltage (Vth), linear-region drain current (Idlin), saturation-region drain current (Idsat), static breakdown voltage (BVoff)), and the drain-to-gate capacitance (Cgd) are shown in Table 1.
In some embodiments, the fabrication method of the gate 14 and the gate extending portion 20 which are substantially in contact with each other is shown. For example, first, a patterned polysilicon layer is formed on the substrate 12. Next, an N-type implantation process is performed on a region (the width thereof is about 0.3 μm) of the patterned polysilicon layer in which the gate 14 is predetermined to be formed, and a P-type implantation process is performed on a region (the width thereof is about 0.35 μm) of the patterned polysilicon layer in which the gate extending portion 20 is predetermined to be formed (as the present embodiment). Optionally, a P-type implantation process is performed on a region (the width thereof is about 0.3 μm) of the patterned polysilicon layer in which the gate 14 is predetermined to be formed, and an N-type implantation process is performed on a region (the width thereof is about 0.35 μm) of the patterned polysilicon layer in which the gate extending portion 20 is predetermined to be formed. So far, the fabrication of the gate 14 and the gate extending portion 20 having opposite doping types and substantially in contact with each other is completed.
TABLE 1
The The The
No P-type semiconductor semiconductor semiconductor
doping on structure of structure of structure of
polysilicon FIG. 3 FIG. 4 FIG. 5
The width of the gate extending portion X/0.5 0.15/0.5 0.25/0.4 0.35/0.3
(μm)/the width of the gate (μm)
The drain-to-gate capacitance (Cgd)(F/μm) 1.63e−15 8.11e−16 3.55e−16 3.10e−16
(Vds = 0 V) (−50.2%) (−78.2%) (−81.0%)
The drain-to-gate capacitance (Cgd)(F/μm) 2.08e−16 1.82e−16 1.76e−16 1.74e−16
(Vds = 1.8 V) (−12.5%) (−15.4%) (−16.3%)
The sum of the width of the gate extending 0.65 0.65 0.65 0.65
portion and the width of the gate (μm)
The threshold voltage (Vth)(V) 0.880 0.880 0.880 0.879
The linear-region drain current (Idlin)(μA) 239 239 239 239
The saturation-region drain current (Idsat)(mA) 4.52 4.52 4.52 4.51
The static breakdown voltage (BVoff)(V) 33.1 33.1 33.1 33.1
As shown in Table 1, under the same operating conditions, as the ratio of the width of the gate extending portion and the width of the gate is gradually increased, the drain-to-gate capacitance is significantly reduced due to the effect of capacitor series connection. For example, when Vds=0V and the ratio of the width of the gate extending portion and the width of the gate is 0.3, the drain-to-gate capacitance of the semiconductor structure of the present invention is reduced by about 50.2% compared to that of the semiconductor structure in which the polysilicon is not P-doped. When the ratio of the width of the gate extending portion and the width of the gate is 0.625, the drain-to-gate capacitance of the semiconductor structure of the present invention is reduced by about 78.2% compared to that of the semiconductor structure in which the polysilicon is not P-doped. When the ratio of the width of the gate extending portion and the width of the gate is 1.17, the drain-to-gate capacitance of the semiconductor structure of the present invention is reduced by about 81% compared to that of the semiconductor structure in which the polysilicon is not P-doped. When Vds=1.8V and the ratio of the width of the gate extending portion and the width of the gate is 0.3, the drain-to-gate capacitance of the semiconductor structure of the present invention is reduced by about 12.5% compared to that of the semiconductor structure in which the polysilicon is not P-doped. When the ratio of the width of the gate extending portion and the width of the gate is 0.625, the drain-to-gate capacitance of the semiconductor structure of the present invention is reduced by about 15.4% compared to that of the semiconductor structure in which the polysilicon is not P-doped. When the ratio of the width of the gate extending portion and the width of the gate is 1.17, the drain-to-gate capacitance of the semiconductor structure of the present invention is reduced by about 16.3% compared to that of the semiconductor structure in which the polysilicon is not P-doped.
Referring to FIG. 6, in accordance with one embodiment of the invention, a semiconductor structure 10 is provided. FIG. 6 is a cross-sectional view of the semiconductor structure 10.
As shown in FIG. 6, the semiconductor structure 10 includes a substrate 12, a gate 14, a source 16, a drain 18, a gate extending portion 20 and a drain drift region 22. The gate 14 is disposed on the substrate 12. The source 16 is disposed in the substrate 12 and located on one side of the gate 14. The drain 18 is disposed in the substrate 12 and located on another side of the gate 14. The gate extending portion 20 is disposed on the substrate 12 and located between the gate 14 and the drain 18. The drain drift region 22 is formed in the substrate 12 and surrounds the drain 18. Specifically, the doping type of the gate 14 is the opposite of that of the gate extending portion 20. For example, when the doping type of the gate 14 is N type, the doping type of the gate extending portion 20 is P type, or when the doping type of the gate 14 is P type, the doping type of the gate extending portion 20 is N type.
In some embodiments, the substrate 12 is a P-type semiconductor substrate or an N-type semiconductor substrate. In some embodiments, when the substrate 12 is a P-type semiconductor substrate, the doping type of the gate 14 is N type, the doping type of the source 16 is N type, the doping type of the drain 18 is N type, and the doping type of the gate extending portion 20 is P type. In some embodiments, when the substrate 12 is an N-type semiconductor substrate, the doping type of the gate 14 is P type, the doping type of the source 16 is P type, the doping type of the drain 18 is P type, and the doping type of the gate extending portion 20 is N type. In some embodiments, the gate 14 and the gate extending portion 20 include polysilicon doped with P-type dopants or polysilicon doped with N-type dopants.
In FIG. 6, the gate 14 is substantially separated from the gate extending portion 20. For example, the gate 14 is substantially separated laterally from the gate extending portion 20 (i.e. the sidewall of the gate 14 is substantially separated from the sidewall of the gate extending portion 20).
In FIG. 6, the gate extending portion 20 is electrically connected with the gate 14 by the metal layer 32. In the present embodiment, the gate extending portion 20 can be considered a metal field plate. In some embodiments, the fabrication method of the gate 14 and the gate extending portion 20 which are substantially separated from each other is shown. For example, first, a patterned polysilicon layer including two separated portions is formed on the substrate 12. Next, an N-type implantation process is performed on the separated portion of the patterned polysilicon layer in which the gate 14 is predetermined to be formed, and a P-type implantation process is performed on the separated portion of the patterned polysilicon layer in which the gate extending portion 20 is predetermined to be formed. Optionally, a P-type implantation process is performed on the separated portion of the patterned polysilicon layer in which the gate 14 is predetermined to be formed, and an N-type implantation process is performed on the separated portion of the patterned polysilicon layer in which the gate extending portion 20 is predetermined to be formed. So far, the fabrication of the gate 14 and the gate extending portion 20 having opposite doping types and substantially separated from each other is completed.
Referring to FIG. 7, in accordance with one embodiment of the invention, a semiconductor structure 10 is provided. FIG. 7 is a cross-sectional view of the semiconductor structure 10.
As shown in FIG. 7, the semiconductor structure 10 includes a substrate 12, a gate 14, a source 16, a drain 18, a gate extending portion 20 and a drain drift region 22. The gate 14 is disposed on the substrate 12. The source 16 is disposed in the substrate 12 and located on one side of the gate 14. The drain 18 is disposed in the substrate 12 and located on another side of the gate 14. The gate extending portion 20 is disposed on the substrate 12 and located between the gate 14 and the drain 18. The drain drift region 22 is formed in the substrate 12 and surrounds the drain 18. Specifically, the doping type of the gate 14 is the opposite of that of the gate extending portion 20. For example, when the doping type of the gate 14 is N type, the doping type of the gate extending portion 20 is P type, or when the doping type of the gate 14 is P type, the doping type of the gate extending portion 20 is N type.
In some embodiments, the substrate 12 is a P-type semiconductor substrate or an N-type semiconductor substrate. In some embodiments, when the substrate 12 is a P-type semiconductor substrate, the doping type of the gate 14 is N type, the doping type of the source 16 is N type, the doping type of the drain 18 is N type, and the doping type of the gate extending portion 20 is P type. In some embodiments, when the substrate 12 is an N-type semiconductor substrate, the doping type of the gate 14 is P type, the doping type of the source 16 is P type, the doping type of the drain 18 is P type, and the doping type of the gate extending portion 20 is N type. In some embodiments, the gate 14 and the gate extending portion 20 include polysilicon doped with P-type dopants or polysilicon doped with N-type dopants.
In FIG. 7, the gate 14 is substantially separated from the gate extending portion 20. For example, the gate 14 is substantially separated laterally from the gate extending portion 20 (i.e. the sidewall of the gate 14 is substantially separated from the sidewall of the gate extending portion 20).
In FIG. 7, the gate extending portion 20 is electrically connected with the source 16 by the metal layer 34. In the present embodiment, the gate extending portion 20 can be considered a metal field plate. In some embodiments, the fabrication method of the gate 14 and the gate extending portion 20 which are substantially separated from each other is shown. For example, first, a patterned polysilicon layer including two separated portions is formed on the substrate 12. Next, an N-type implantation process is performed on the separated portion of the patterned polysilicon layer in which the gate 14 is predetermined to be formed, and a P-type implantation process is performed on the separated portion of the patterned polysilicon layer in which the gate extending portion 20 is predetermined to be formed. Optionally, a P-type implantation process is performed on the separated portion of the patterned polysilicon layer in which the gate 14 is predetermined to be formed, and an N-type implantation process is performed on the separated portion of the patterned polysilicon layer in which the gate extending portion 20 is predetermined to be formed. So far, the fabrication of the gate 14 and the gate extending portion 20 having opposite doping types and substantially separated from each other is completed.
In the present invention, two regions with opposite doping types (for example, the region adjacent to the drain is P-type doped (defined as the gate extending portion), and the region away from the drain is N-type doped (defined as the gate)) are formed in the polysilicon gate of a MOS transistor using implantation processes. Due to the effect of capacitor series connection, the drain-to-gate capacitance is reduced. As the ratio of the width of the gate extending portion and the width of the gate increases, the drain-to-gate capacitance decreases more obviously. At this time, the gate extending portion has the function of field plate, which can effectively disperse the electric field strength of the drain region (the drift region) and prevent the component from being damaged in a high-voltage operation environment. In addition, the two regions having opposite doping types can be fabricated into two separated structures. On the one hand, the gate extending portion can have the function of field plate, and on the other hand, the effect of reducing the drain-to-gate capacitance can be achieved. The cost of the present invention is low, and it is easily fabricated without changing the existing MOS process specifications. Due to the dropping in the drain-to-gate capacitance, undesired current flow caused by the coupling effect of the transistor is avoided. The specific semiconductor structure design of the present invention can effectively reduce the power loss of the switching components, greatly improving the switching frequency and achieving high-efficiency electric power conversion.
While the invention has been described by way of example and in terms of preferred embodiment, it should be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
