Abstract: A delay line for a printed circuit board (PCB) is disclosed. The delay line includes a first straight line, a second straight line and a third straight line. The second and third straight lines are respectively disposed at two sides of the first straight line. The first, second and third straight lines are parallel to each other and form a delay path. The current direction of the second straight line is opposite to that of the third straight line.

Abstract: A non-volatile memory storage device has a non-volatile memory, e.g., a flash memory, and a controller coupled to the non-volatile memory. The controller comprises a plurality of control circuits and an arbitration circuit. Each control circuit is configured to generate a request to update the chip-enable (CE) signals for non-volatile memory, and the arbitration circuit is configured to determine when the requests are acknowledged. The arbitration circuit generates acknowledge signals to the control circuits when all of the requests of the control circuits have been received by the arbitration circuit. The CE signals for non-volatile memory are updated when requests are acknowledged.

Abstract: A heat-dissipating mechanism includes a first heat-dissipating device, a first positioning device, a second heat-dissipating device and a second positioning device. The first heat-dissipating device is contacted with a memory module. The first positioning device is disposed on the first heat-dissipating device and includes a protrusion. The second heat-dissipating device is connected with the first heat-dissipating device. The second positioning device has a positioning rail formed in the second heat-dissipating device and corresponding to the protrusion. The second heat-dissipating device is connected with the first heat-dissipating device when the protrusion of the first positioning device is embedded into the positioning rail second positioning device.

Abstract: A method for evaluating a temperature rise of a printed circuit board (PCB) trace receives a plurality of attribute parameters of the PCB trace. A temperature rise formula is determined for the PCB trace. The method further calculates the temperature rise by applying the temperature rise formula, and outputs the temperature rise.

Abstract: A method for improving EBG (electromagnetic bandgap) structures is provided. First, a multi-layer board having at least one EBG unit is provided. Then, a maximum input impedance of the EBG unit under a predetermined frequency band is measured, in which a frequency corresponding to the maximum input impedance is a resonance frequency, and a capacitance is determined based on the resonance frequency. Besides, a minimum input impedance of the EBG unit is measured, and a logarithmic value corresponding to the maximum input impedance and a logarithmic value corresponding to the minimum input impedance are obtained so as to determine a resistance. Finally, an electronic device having the capacitance and the resistance is coupled to the EBG unit in parallel.

Abstract: A method for copying data in a non-volatile memory system is disclosed. The method includes calculating a number of errors of a first set of data from a source block of the non-volatile memory saved in the buffer of the controller, transmitting the first set of data saved in the buffer of the controller to a buffer of the non-volatile memory when the number of errors is lower than a threshold, and programming a destination block of the non-volatile memory with the first set of data saved in the buffer of the non-volatile memory when the number of errors is lower than the threshold.

Abstract: A non-volatile memory system and a method for reading data therefrom are provided. The data comprises a first sub-data and a second sub-data. The non-volatile memory system comprises a first storage unit and a second storage unit, adapted for storing the two sub-data respectively. The first storage unit reads a first command from the controller, and stores the first sub-data temporarily as the first temporary sub-data according to the first command. The second storage unit reads a second command from the controller, and stores the second sub-data temporarily as the second temporary sub-data according to the second command. The first temporary sub-data is read from the first storage unit. Then, the first storage unit reads a third command from the controller. The second temporary sub-data is also read from the second storage unit while reading the third command. The time for reading data from the non-volatile memory system is reduced.

Abstract: A positive differential signal trace and a negative differential signal trace are formed on different layers of a printed circuit board. A first ground trace is formed on the layer on which the positive differential signal trace is formed, and a second ground trace is formed on the layer on which the negative differential signal trace is formed. An insulation layer is positioned between the two layers and has a predetermined thickness. A differential mode impedance and a common mode impedance of differential signals are dependent on the predetermined thickness of the insulation layer, width and thickness of each differential signal trace, and a space between each differential signal trace and the corresponding ground trace formed on the same layer.

Abstract: An electrical test device including a substrate and a plurality of test pads. The test pads are disposed on a second surface of the substrate. Each test pad has a test hole, and first and second isolation slots. The first isolation slot is disposed on the periphery of the test hole, and defines a signal region for connecting a signal terminal of a test probe. The second isolation slot is disposed on the periphery of the first isolation slot, and a ground region is defined between the first and second isolation slots. The ground region is used for connecting a ground terminal of the test probe. The test pad can match with the test probe so that the test probe can connect to the test pad for providing signal to the test probe. The electrical test device can easily measure the real electrical characteristic of the signal from the substrate.

Abstract: This invention discloses an audio process circuit structure and process method applying to a video/audio apparatus that at least comprises an audio signal detection unit, an OR gate logic circuit unit, an AND gate logic circuit unit and an audio amplifier process unit. The audio signal detection unit also comprises a coupling capacitor, a signal amplifier circuit, a DC level shift circuit, a charge circuit and a switch circuit. This audio signal detection unit transfers different amplitude and frequency of the signal to be a high or low DC logic level signal. The high DC logic level signal is an audio signal and the low DC logic level signal is a noise. When the noise is inputted to the audio signal detection unit and a mute control signal is outputted by the audio signal detection unit to disable the audio amplifier process unit so as to prohibit the noise to output.

Abstract: This invention discloses a POP noise processing circuit structure applying to an output apparatus. Therein, the output apparatus is a panel display apparatus. The POP noise processing circuit structure comprises at least one first processing unit, a second processing unit, an operational amplifier processing unit, and an audio POP noise processing unit. The first processing unit provides an audio signal to the operational amplifier processing unit, and the second processing unit provides a system signal to the audio POP noise processing unit that provides a mute signal to the operational amplifier processing unit. When the output apparatus is in a shutdown mode or a mute mode, the audio signal includes a high voltage pulse, and utilizes the circuit characteristic of the audio POP noise processing unit to eliminate the POP noise caused from the high voltage pulse.

Abstract: The invention relates to an electrical test device having isolation slot. The electrical test device comprises a substrate and a plurality of test pads. The test pads are disposed on a second surface of the substrate. Each test pads has a test hole, a first isolation slot and a second isolation slot. The first isolation slot is disposed on the periphery of the test hole, and defines a signal region for connecting a signal terminal of a test probe. The second isolation slot is disposed on the periphery of the first isolation slot, and a ground region is defined between the first isolation slot and the second isolation slot. The ground region is used for connecting a ground terminal of the test probe. The test pad of the invention can match with the test probe so that the test probe can connect to the test pad for providing signal to the test probe. Therefore, the electrical test device can be utilized to easily measure the real electrical characteristic of the signal from the substrate.

Abstract: A multi-chip package with electrical interconnection comprises a leadframe, at least a relay conductor, at least a first chip, at least a second chip, a plurality of bonding wires and a molding compound. A dielectric carrier is attached to the leadframe for fixing the relay conductor. The relay conductor has a top surface for interconnection of the bonding wires and a bottom surface attached to the dielectric carrier to electrically isolated from the leadframe. The bonding wires electrically connect the bonding pads of the first chip and second chip to the common lead of the leadframe through the relay conductor so as to achieve electrical interconnection of the plurality of chips and the leadframe inside the molding compound with lower cost.

Abstract: A multi-chip package with electrical interconnection comprises a leadframe, at least a relay conductor, at least a first chip, at least a second chip, a plurality of bonding wires and a molding compound. A dielectric carrier is attached to the leadframe for fixing the relay conductor. The relay conductor has a top surface for interconnection of the bonding wires and a bottom surface attached to the dielectric carrier to electrically isolated from the leadframe. The bonding wires electrically connect the bonding pads of the first chip and second chip to the common lead of the leadframe through the relay conductor so as to achieve electrical interconnection of the plurality of chips and the leadframe inside the molding compound with lower cost.

Abstract: A holding apparatus for an optical integration rod is installed outside of an optical integration rod. It comprises a holder which is a heat sink substrate with fins disposed at the outside surface thereof. A thermal conductivity material is filled in between the holding apparatus and the optical integration rod to allow the heat yielded in the rod to be guided out through the thermal conductivity material and then to be transmitted to the holder to carry away by way of a natural or forced convection manner so as to attain to a heat dissipation effect. Because the holder has a broader heat exchange area and the heat conduction function of the thermal conductivity material is better than air, the heat contact resistance between the holder and the rod can be reduced so as to enhance the heat dissipation efficiency.