Patents by Inventor Chih-Wei Yang
Chih-Wei Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10283616Abstract: A fabricating method of a semiconductor structure includes the following steps. A gate material layer is formed on a semiconductor substrate. A patterned mask layer is formed on the gate material layer. The pattern mask layer includes at least one opening exposing a part of the gate material layer. An impurity treatment is performed to the gate material layer partially covered by the pattern mask layer for forming at least one doped region in the gate material layer. An etching process is performed to remove the gate material layer including the doped region. A dummy gate may be formed by patterning the gate material layer, and the impurity treatment may be performed after the step of forming the dummy gate. The performance of the etching processes for removing the gate material layer and/or the dummy gate may be enhanced, and the gate material residue issue may be solved accordingly.Type: GrantFiled: August 30, 2016Date of Patent: May 7, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wen-Chien Hsieh, En-Chiuan Liou, Chih-Wei Yang, Yu-Cheng Tung, Po-Wen Su
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Patent number: 10283413Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure, and a spacer. The semiconductor substrate includes at least one fin structure. The isolation structure is partly disposed in the fin structure and partly disposed above the fin structure. The fin structure includes a first fin and a second fin elongated in the same direction. A part of the isolation structure is disposed between the first fin and the second fin in the direction where the first fin and the second fin are elongated. The spacer is disposed on sidewalls of the isolation structure on the fin structure. The isolation structure in the present invention is partly disposed in the fin structure and partly disposed above the fin structure. The negative influence of a gate structure formed on the isolation structure and sinking into the isolation structure on the isolation performance of the isolation structure may be avoided accordingly.Type: GrantFiled: September 13, 2016Date of Patent: May 7, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: En-Chiuan Liou, Yu-Cheng Tung, Chih-Wei Yang
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Patent number: 10249729Abstract: A method for fabricating a semiconductor device. After forming SiGe epitaxial layer within the Core_p region, the hard mask is removed. A contact etch stop layer (CESL) is deposited on the composite spacer structure and the epitaxial layer. An ILD layer is deposited on the CESL. The ILD layer is polished to expose a top surface of the dummy gate. The dummy gate and a first portion of the first nitride-containing layer of the composite spacer structure are removed, thereby forming a gate trench and exposing the first gate dielectric layer. The first gate dielectric layer is removed from the gate trench, and a second portion of the first nitride-containing layer and the oxide layer are removed from the composite spacer structure, while leaving the second nitride-containing layer intact.Type: GrantFiled: December 5, 2017Date of Patent: April 2, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ying-Hsien Chen, Chun-Chia Chen, Yao-Jhan Wang, Chih-wei Yang, Te-Chang Hsu
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Publication number: 20190081150Abstract: The present invention provides a method for forming a semiconductor structure, including the following steps: first, a substrate is provided, an interlayer dielectric (ILD) is formed on the substrate, a first dummy gate is formed in the ILD, wherein the first dummy gate includes a dummy gate electrode and two spacers disposed on two sides of the dummy gate electrode respectively. Next, two contact holes are formed in the ILD at two sides of the first dummy gate respectively. Afterwards, the dummy gate electrode is removed, so as to form a gate recess in the ILD, a first material layer is filled in the gate recess and a second material layer is filled in the two contact holes respectively, and an anneal process is performed on the first material layer and the second material layer, to bend the two spacers into two inward curving spacers.Type: ApplicationFiled: November 1, 2018Publication date: March 14, 2019Inventors: En-Chiuan Liou, Yu-Cheng Tung, Rung-Yuan Lee, Chih-Wei Yang
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Patent number: 10191614Abstract: A panel displaying method for an electronic device is provided. The electronic device includes a display module and has a plurality of first icons corresponding to a plurality of objects. The panel displaying method includes: determining an environment of the electronic device; automatically choosing an operation mode based on the environment of the electronic device. The operation mode is displayed in a widget area of a first panel and includes at least one widget icon. A portion of the first icons is chosen and updated as the widget icon based on numbers of clicks of the first icons in the chosen operation mode. Moreover, a portable electronic device and a recording medium using the method are also provided.Type: GrantFiled: February 23, 2016Date of Patent: January 29, 2019Assignee: HTC CorporationInventors: Shawna Julie Davis, Kuang-Ting Chuang, Shih-Pin Lin, Chia-Hung Kao, Chia-Yuan Chang, Chih-Wei Yang
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Patent number: 10164039Abstract: A semiconductor device having metal gate includes a substrate, a metal gate formed on the substrate, a pair of spacers formed on sidewalls of the metal gate, a contact etch stop layer (CESL) covering the spacers, an insulating cap layer formed on the metal gate, the spacers and the CESL, and an ILD layer surrounding the metal gate, the spacers, the CESL and the insulating cap layer. The metal gate, the spacers and the CESL include a first width, and the insulating cap layer includes a second width. The second width is larger than the first width. And a bottom of the insulating cap layer concurrently contacts the metal gate, the spacers, the CESL, and the ILD layer.Type: GrantFiled: October 3, 2016Date of Patent: December 25, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: En-Chiuan Liou, Chih-Wei Yang, Yu-Cheng Tung
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Patent number: 10153353Abstract: The present invention provides a method for forming a semiconductor structure, including the following steps: first, a substrate is provided, an interlayer dielectric (ILD) is formed on the substrate, a first dummy gate is formed in the ILD, wherein the first dummy gate includes a dummy gate electrode and two spacers disposed on two sides of the dummy gate electrode respectively. Next, two contact holes are formed in the ILD at two sides of the first dummy gate respectively. Afterwards, the dummy gate electrode is removed, so as to form a gate recess in the ILD, a first material layer is filled in the gate recess and a second material layer is filled in the two contact holes respectively, and an anneal process is performed on the first material layer and the second material layer, to bend the two spacers into two inward curving spacers.Type: GrantFiled: June 5, 2017Date of Patent: December 11, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: En-Chiuan Liou, Yu-Cheng Tung, Rung-Yuan Lee, Chih-Wei Yang
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Publication number: 20180350934Abstract: The present invention provides a method for forming a semiconductor structure, including the following steps: first, a substrate is provided, an interlayer dielectric (ILD) is formed on the substrate, a first dummy gate is formed in the ILD, wherein the first dummy gate includes a dummy gate electrode and two spacers disposed on two sides of the dummy gate electrode respectively. Next, two contact holes are formed in the ILD at two sides of the first dummy gate respectively. Afterwards, the dummy gate electrode is removed, so as to form a gate recess in the ILD, a first material layer is filled in the gate recess and a second material layer is filled in the two contact holes respectively, and an anneal process is performed on the first material layer and the second material layer, to bend the two spacers into two inward curving spacers.Type: ApplicationFiled: June 5, 2017Publication date: December 6, 2018Inventors: En-Chiuan Liou, Yu-Cheng Tung, Rung-Yuan Lee, Chih-Wei Yang
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Patent number: 10134629Abstract: A method for manufacturing a semiconductor structure includes the following steps. At first, a titanium layer is formed on a preformed layer. Then, a first titanium nitride layer is formed on the titanium layer. A first plasma treatment is applied to the first titanium nitride layer such that the first titanium nitride layer has a first N/Ti ratio. A second titanium nitride layer is formed on the first titanium nitride layer. A second plasma treatment is applied to the second titanium nitride layer such that the second titanium nitride layer has a second N/Ti ratio larger than the first N/Ti ratio.Type: GrantFiled: September 6, 2017Date of Patent: November 20, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ching-Wen Hung, Yen-Tsai Yi, Wei-Chuan Tsai, En-Chiuan Liou, Chih-Wei Yang
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Publication number: 20180261589Abstract: An integrated circuit process includes the following steps. A substrate including a first area and a second area is provided. A plurality of line patterns cover the substrate of the first area, and a sacrificial line pattern covers the substrate of the second area, wherein these line patterns separate from and are orthogonal to the sacrificial line pattern. The present invention also provides an integrated circuit formed by said process. A substrate includes a first area and a second area; a plurality of line patterns cover the substrate of the first area; a slot pattern is in the substrate of the second area, wherein these line patterns are orthogonal to the slot pattern. Additionally, a plurality of line patterns cover the substrate; a sacrificial line pattern is at ends of the line patterns, wherein these line patterns separate from and are orthogonal to the sacrificial line pattern.Type: ApplicationFiled: May 16, 2018Publication date: September 13, 2018Inventors: En-Chiuan Liou, Chih-Wei Yang, Kuei-Chun Hung
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Patent number: 10019154Abstract: A method, an apparatus and a computer program product for operating items with multiple fingers, adapted to a portable apparatus having a touch screen, are provided. In the method, a first touch operation performed on at least one item displayed on the touch screen is detected. A time of the first touch operation staying on the at least one item is accumulated and determined whether to be over a threshold. When the staying time is over the threshold, an edit mode of the item is entered and a second touch operation performed on the touch screen is detected. Finally, the at least one item is operated according to the first touch operation and the second touch operation.Type: GrantFiled: January 21, 2016Date of Patent: July 10, 2018Assignee: HTC CorporationInventors: Ching-Tung Liu, Hsueh-Chun Chen, Chih-Wei Yang, Wei-Nien Shih
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Patent number: 9991337Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region; forming a plurality of fin-shaped structures and a first shallow trench isolation (STI) around the fin-shaped structures on the first region and the second region; forming a patterned hard mask on the second region; removing the fin-shaped structures and the first STI from the first region; forming a second STI on the first region; removing the patterned hard mask; and forming a gate structure on the second STI.Type: GrantFiled: August 30, 2015Date of Patent: June 5, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: En-Chiuan Liou, Chih-Wei Yang, Yu-Cheng Tung, Chun-Yuan Wu
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Patent number: 9965138Abstract: A method of activating an update of a home screen of a mobile communications device is provided. The home screen is displayed on a display panel of the mobile communications device. The home screen includes a plurality of tiles displaying a plurality of feeds from one or more feed sources. The method includes performing one of updating the home screen or activating and displaying a menu bar on the display panel based on a distance of a downward scrolling on a top page of a home screen. A non-transitory computer-readable medium and a mobile communications device for activating an update of a home screen of a mobile communications device are also provided.Type: GrantFiled: October 2, 2013Date of Patent: May 8, 2018Assignee: HTC CORPORATIONInventors: Drew Bamford, David Brinda, Peter Chin, Jesse John Penico, Chih-Wei Yang, Huai-Ting Huang
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Patent number: 9933821Abstract: An apparatus may include a chassis that can receive a sled and a locking mechanism. The locking mechanism can mechanically lock the sled to the chassis to prevent a sudden power loss that can be caused from an unexpected removal of the sled from the chassis. To avoid a sudden power loss, a voltage-sensing electrical switch lock can be implemented to the chassis to mechanically lock the sled to the chassis until the sled is ready to be removed. The sled may include one or more computing devices that need to be inactive before removing the sled. The apparatus includes a controller that may detect whether at least one of computing devices in the sled are in an active state or in an inactive state. Based on the determination of the state of the computing devices in the sled, the controller may activate the locking mechanism or de-active locking mechanism.Type: GrantFiled: February 17, 2016Date of Patent: April 3, 2018Assignee: QUANTA COMPUTER INC.Inventors: Jen-Hsuen Huang, Fa-Da Lin, Chih-Wei Yu, Chih-Wei Yang
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Publication number: 20180061963Abstract: A fabricating method of a semiconductor structure includes the following steps. A gate material layer is formed on a semiconductor substrate. A patterned mask layer is formed on the gate material layer. The pattern mask layer includes at least one opening exposing a part of the gate material layer. An impurity treatment is performed to the gate material layer partially covered by the pattern mask layer for forming at least one doped region in the gate material layer. An etching process is performed to remove the gate material layer including the doped region. A dummy gate may be formed by patterning the gate material layer, and the impurity treatment may be performed after the step of forming the dummy gate. The performance of the etching processes for removing the gate material layer and/or the dummy gate may be enhanced, and the gate material residue issue may be solved accordingly.Type: ApplicationFiled: August 30, 2016Publication date: March 1, 2018Inventors: Wen-Chien Hsieh, En-Chiuan Liou, Chih-Wei Yang, Yu-Cheng Tung, Po-Wen Su
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Publication number: 20180053761Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate including at least one fin structure is provided. A gate material layer is formed on the semiconductor substrate, and the fin structure is covered by the gate material layer. A trench is formed partly in the gate material layer and partly in the fin structure. An isolation structure is formed partly in the trench and partly outside the trench. At least one gate structure is formed straddling the fin structure by patterning the gate material layer after the step of forming the isolation structure. A top surface of the isolation structure is higher than a top surface of the gate structure in a vertical direction for enhancing the isolation performance of the isolation structure. A sidewall spacer is formed on sidewalls of the isolation structure, and there is no gate structure formed on the isolation structure.Type: ApplicationFiled: August 21, 2016Publication date: February 22, 2018Inventors: En-Chiuan Liou, Yu-Cheng Tung, Chih-Wei Yang
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Publication number: 20180047635Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure, and a spacer. The semiconductor substrate includes at least one fin structure. The isolation structure is partly disposed in the fin structure and partly disposed above the fin structure. The fin structure includes a first fin and a second fin elongated in the same direction. A part of the isolation structure is disposed between the first fin and the second fin in the direction where the first fin and the second fin are elongated. The spacer is disposed on sidewalls of the isolation structure on the fin structure. The isolation structure in the present invention is partly disposed in the fin structure and partly disposed above the fin structure. The negative influence of a gate structure formed on the isolation structure and sinking into the isolation structure on the isolation performance of the isolation structure may be avoided accordingly.Type: ApplicationFiled: September 13, 2016Publication date: February 15, 2018Inventors: En-Chiuan Liou, Yu-Cheng Tung, Chih-Wei Yang
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Patent number: 9891781Abstract: A method of navigating between a plurality of different views of a home screen of a mobile communications device is provided. The mobile communications device includes a home button, a processor, and a display panel configured to cooperate with the processor to display one of the views of the home screen. The method includes selectively displaying one of the views of the home screen on the display panel based on a number of times the home button is activated within a predetermined time period. A non-transitory computer-readable medium and a mobile communications device of navigating between a plurality of different views of a home screen of a mobile communications device are also provided.Type: GrantFiled: October 2, 2013Date of Patent: February 13, 2018Assignee: HTC CORPORATIONInventors: Drew Bamford, David Brinda, Peter Chin, Jesse John Penico, Chih-Wei Yang, Huai-Ting Huang
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Publication number: 20180040693Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a plurality of fin-shaped structures and a first shallow trench isolation (STI) around the fin-shaped structures on the first region and the second region; forming a patterned hard mask on the second region; removing the fin-shaped structures and the first STI from the first region; forming a second STI on the first region; removing the patterned hard mask; and forming a gate structure on the second STI.Type: ApplicationFiled: October 18, 2017Publication date: February 8, 2018Inventors: En-Chiuan Liou, Chih-Wei Yang, Yu-Cheng Tung, Chun-Yuan Wu
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Patent number: 9875928Abstract: A method for fabricating metal interconnect structure is disclosed. The method includes the steps of: providing a substrate having a first inter-metal dielectric (IMD) layer thereon; forming a metal interconnection in the first IMD layer; removing part of the first IMD layer; forming a spacer adjacent to the metal interconnection; and using the spacer as mask to remove part of the first IMD layer for forming an opening in the first IMD layer.Type: GrantFiled: April 9, 2015Date of Patent: January 23, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: En-Chiuan Liou, Yu-Cheng Tung, Chih-Wei Yang