Abstract: A heat dissipation assembly is disclosed and includes a fan, a vapor chamber and a heat dissipation fin set. The fan includes a fan frame, an impeller and a fan cover. The impeller is disposed on the fan frame and accommodated in an accommodation space. The impeller includes plural metal blades and a hub, and the plural metal blades are radially arranged on the periphery of the hub to form a dense-metal-blade impeller. The fan cover is assembled with the fan frame to form an outlet, and the fan cover includes an inlet. The vapor chamber includes an upper plate and a lower plate assembled with each other. The upper plate or the lower plate is connected to the fan cover, and the vapor chamber and the fan cover are coplanar. The heat dissipation fin set is connected to the lower plate and spatially corresponding to the outlet.

Abstract: A method for fabricating a resistor structure includes the steps of forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, patterning the p-type semiconductor layer, trimming the barrier layer along a first direction, and then forming an electrode on the barrier layer along a second direction.

Abstract: A waterproof container is adapted for an electronic device with a touch screen. The waterproof container includes an upper component and a lower component. The upper component includes a first layer, a second layer and a third layer. The second layer is disposed between the first layer and the third layer. A second touched part of the second layer is connected to a first touched part of the first layer by a plurality of first connections. The second touched part of the second layer is connected to a third touched part of the third layer by a plurality of second connections, and the plurality of first connections and the plurality of second connections are staggered relative to each other. The lower component is connected to the upper component. An accommodating space is enclosed by the lower component and the upper component for accommodating the electronic device.

Abstract: A sealing bag includes a bag body and a sealing system including an elastomeric protruding component and a covering assembly. The elastomeric protruding component is disposed on the bag body and protrudes from the bag body along a protruding direction. A slit penetrates through the elastomeric protruding component along the protruding direction and is communicated with an inner space of the bag body. The covering assembly includes a covering component including a first covering portion detachably installed on the elastomeric protruding component in a sliding manner, and a second covering portion pivotally connected to the first covering portion. The second covering portion drives the first covering portion to squeeze the elastomeric protruding component along a lateral direction different from the protruding direction to seal the slit when the first covering portion is installed on the elastomeric protruding component and the second covering portion pivotally engages with the first covering portion.

Abstract: A method for fabricating an one time programmable (OTP) device includes the steps of: forming a first gate structure and a second gate structure extending along a first direction on a substrate; forming a diffusion region adjacent to two sides of the first gate structure and the second gate structure; forming a silicide layer adjacent to the first gate structure; and patterning the first gate structure for forming a third gate structure and a fourth gate structure.

Abstract: An integrated circuit process includes the following steps. A substrate including a first area and a second area is provided. A plurality of line patterns cover the substrate of the first area, and a sacrificial line pattern covers the substrate of the second area, wherein these line patterns separate from and are orthogonal to the sacrificial line pattern. The present invention also provides an integrated circuit formed by said process. A substrate includes a first area and a second area; a plurality of line patterns cover the substrate of the first area; a slot pattern is in the substrate of the second area, wherein these line patterns are orthogonal to the slot pattern. Additionally, a plurality of line patterns cover the substrate; a sacrificial line pattern is at ends of the line patterns, wherein these line patterns separate from and are orthogonal to the sacrificial line pattern.

Abstract: A sealing bag includes a bag body and a sealing system. The sealing system includes an elastomeric protruding component and a covering assembly. The elastomeric protruding component is disposed on the bag body and protruding from the bag body along a protruding direction. A slit penetrates through the elastomeric protruding component along the protruding direction and is communicated with an inner space of the bag body. The covering assembly is for detachably engaging with the elastomeric protruding component. The covering assembly squeezes the elastomeric protruding component along the protruding direction and a lateral direction different from the protruding direction to seal the slit when the covering assembly engages with the elastomeric protruding component. Such mechanism can ensure nothing goes in or comes out when the slit is sealed. Therefore, the present invention has enhanced reliability.

Abstract: A sealing bag includes a bag body and a sealing system including an elastomeric protruding component and a covering assembly. The elastomeric protruding component is disposed on the bag body and protrudes from the bag body along a protruding direction. A slit penetrates through the elastomeric protruding component along the protruding direction and is communicated with an inner space of the bag body. The covering assembly includes a covering component including a first covering portion detachably installed on the elastomeric protruding component in a sliding manner, and a second covering portion pivotally connected to the first covering portion. The second covering portion drives the first covering portion to squeeze the elastomeric protruding component along a lateral direction different from the protruding direction to seal the slit when the first covering portion is installed on the elastomeric protruding component and the second covering portion pivotally engages with the first covering portion.

Abstract: A fabricating method of a semiconductor structure includes the following steps. A gate material layer is formed on a semiconductor substrate. A patterned mask layer is formed on the gate material layer. The pattern mask layer includes at least one opening exposing a part of the gate material layer. An impurity treatment is performed to the gate material layer partially covered by the pattern mask layer for forming at least one doped region in the gate material layer. An etching process is performed to remove the gate material layer including the doped region. A dummy gate may be formed by patterning the gate material layer, and the impurity treatment may be performed after the step of forming the dummy gate. The performance of the etching processes for removing the gate material layer and/or the dummy gate may be enhanced, and the gate material residue issue may be solved accordingly.

Abstract: A sealing bag includes a bag body and a sealing system. The sealing system includes an elastomeric protruding component and a covering assembly. The elastomeric protruding component is disposed on the bag body and protruding from the bag body along a protruding direction. A slit penetrates through the elastomeric protruding component along the protruding direction and is communicated with an inner space of the bag body. The covering assembly is for detachably engaging with the elastomeric protruding component. The covering assembly squeezes the elastomeric protruding component along the protruding direction and a lateral direction different from the protruding direction to seal the slit when the covering assembly engages with the elastomeric protruding component. Such mechanism can ensure nothing goes in or comes out when the slit is sealed. Therefore, the present invention has enhanced reliability.

Abstract: An electronic device operating in standby mode is provided. The electronic device includes a power supply unit, a cooling device coupled to the power supply unit, at least one electronic component cooled by the cooling device, and a controller coupled to the cooling device. The controller is operable to periodically monitor power data and the temperature of the at least one electronic component in standby mode. The controller is also operable to regulate power supplied to the cooling device based on the monitored power data and the temperature of the at least one electronic component.

Abstract: An apparatus for dynamic thermal control is provided. The apparatus includes a fan module with multiple fan units, a deflection member configured to direct airflow received from the fan module, and a system component. The apparatus also includes a chassis management controller (CMC). The CMC is coupled to the fan module, deflection member, and the system component. The CMC is configured to dynamically control the deflection member to direct airflow from the fan module to the system component by accounting for at least one environmental element within the apparatus.

Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate including at least one fin structure is provided. A gate material layer is formed on the semiconductor substrate, and the fin structure is covered by the gate material layer. A trench is formed partly in the gate material layer and partly in the fin structure. An isolation structure is formed partly in the trench and partly outside the trench. At least one gate structure is formed straddling the fin structure by patterning the gate material layer after the step of forming the isolation structure. A top surface of the isolation structure is higher than a top surface of the gate structure in a vertical direction for enhancing the isolation performance of the isolation structure. A sidewall spacer is formed on sidewalls of the isolation structure, and there is no gate structure formed on the isolation structure.

Abstract: A system and method for compensating for voltage drops in a device having a remote node is disclosed. A power supply unit has an adjustable voltage output and a feedback circuit. A power path is coupled to the power supply unit to supply voltage to the remote node. A switch has an output coupled to the feedback circuit, a first input coupled to the power path, and a second input coupled to the remote node. A controller is coupled to the switch. The controller is operable to control the switch to switch between the inputs to cause the feedback circuit of the power supply unit to compensate the voltage output for a voltage drop on the power path or the remote node.

Abstract: The present invention provides a method for forming a dynamic random access memory (DRAM) structure, the method including: firstly, a substrate is provided, a cell region and a peripheral region are defined on the substrate, a plurality of buried word lines is then formed in the cell region of the substrate, next, a shallow trench isolation structure is formed in the peripheral region adjacent to the cell region, wherein a concave top surface is formed on the shallow trench isolation structure, afterwards, a first dummy bit line gate is formed within the shallow trench isolation structure of the peripheral area, and a second dummy bit line gate is formed in the cell region and adjacent to the first dummy bit line gate, wherein a top surface of the first dummy bit line gate is lower than a top surface of the second dummy bit line gate.

Abstract: A system and method for detecting and compensating for temperature effects in a device having a power supply and a remote node. The system includes a power supply unit having an adjustable voltage output and a feedback circuit. The voltage output is adjusted based on the output of the feedback circuit. A power path is coupled to the power supply unit. The power path has power connectors to supply voltage from the power supply unit to a remote node. The remote node is operable to sense a voltage drop of the power path at the remote node associated with temperature effects on the power connectors. An adjustable resistor has an output coupled to the feedback circuit. A controller is coupled to the remote node and the adjustable resistor. The controller determines a resistance value to compensate for the temperature effects and sets the adjustable resistor to change the power output.

Abstract: A system and method for compensating for voltage drops in a device having a remote node is disclosed. A power supply unit has an adjustable voltage output and a feedback circuit. A power path is coupled to the power supply unit to supply voltage to the remote node. A switch has an output coupled to the feedback circuit, a first input coupled to the power path, and a second input coupled to the remote node. A controller is coupled to the switch. The controller is operable to control the switch to switch between the inputs to cause the feedback circuit of the power supply unit to compensate the voltage output for a voltage drop on the power path or the remote node.

Abstract: The present invention provides a method for forming a dynamic random access memory (DRAM) structure, the method including: firstly, a substrate is provided, a cell region and a peripheral region are defined on the substrate, a plurality of buried word lines is then formed in the cell region of the substrate, next, a shallow trench isolation structure is formed in the peripheral region adjacent to the cell region, wherein a concave top surface is formed on the shallow trench isolation structure, afterwards, a first dummy bit line gate is formed within the shallow trench isolation structure of the peripheral area, and a second dummy bit line gate is formed in the cell region and adjacent to the first dummy bit line gate, wherein a top surface of the first dummy bit line gate is lower than a top surface of the second dummy bit line gate.