Patents by Inventor Chih-Wei Yang

Chih-Wei Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10019154
    Abstract: A method, an apparatus and a computer program product for operating items with multiple fingers, adapted to a portable apparatus having a touch screen, are provided. In the method, a first touch operation performed on at least one item displayed on the touch screen is detected. A time of the first touch operation staying on the at least one item is accumulated and determined whether to be over a threshold. When the staying time is over the threshold, an edit mode of the item is entered and a second touch operation performed on the touch screen is detected. Finally, the at least one item is operated according to the first touch operation and the second touch operation.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: July 10, 2018
    Assignee: HTC Corporation
    Inventors: Ching-Tung Liu, Hsueh-Chun Chen, Chih-Wei Yang, Wei-Nien Shih
  • Patent number: 9991337
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region; forming a plurality of fin-shaped structures and a first shallow trench isolation (STI) around the fin-shaped structures on the first region and the second region; forming a patterned hard mask on the second region; removing the fin-shaped structures and the first STI from the first region; forming a second STI on the first region; removing the patterned hard mask; and forming a gate structure on the second STI.
    Type: Grant
    Filed: August 30, 2015
    Date of Patent: June 5, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Chih-Wei Yang, Yu-Cheng Tung, Chun-Yuan Wu
  • Patent number: 9965138
    Abstract: A method of activating an update of a home screen of a mobile communications device is provided. The home screen is displayed on a display panel of the mobile communications device. The home screen includes a plurality of tiles displaying a plurality of feeds from one or more feed sources. The method includes performing one of updating the home screen or activating and displaying a menu bar on the display panel based on a distance of a downward scrolling on a top page of a home screen. A non-transitory computer-readable medium and a mobile communications device for activating an update of a home screen of a mobile communications device are also provided.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: May 8, 2018
    Assignee: HTC CORPORATION
    Inventors: Drew Bamford, David Brinda, Peter Chin, Jesse John Penico, Chih-Wei Yang, Huai-Ting Huang
  • Patent number: 9933821
    Abstract: An apparatus may include a chassis that can receive a sled and a locking mechanism. The locking mechanism can mechanically lock the sled to the chassis to prevent a sudden power loss that can be caused from an unexpected removal of the sled from the chassis. To avoid a sudden power loss, a voltage-sensing electrical switch lock can be implemented to the chassis to mechanically lock the sled to the chassis until the sled is ready to be removed. The sled may include one or more computing devices that need to be inactive before removing the sled. The apparatus includes a controller that may detect whether at least one of computing devices in the sled are in an active state or in an inactive state. Based on the determination of the state of the computing devices in the sled, the controller may activate the locking mechanism or de-active locking mechanism.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: April 3, 2018
    Assignee: QUANTA COMPUTER INC.
    Inventors: Jen-Hsuen Huang, Fa-Da Lin, Chih-Wei Yu, Chih-Wei Yang
  • Publication number: 20180061963
    Abstract: A fabricating method of a semiconductor structure includes the following steps. A gate material layer is formed on a semiconductor substrate. A patterned mask layer is formed on the gate material layer. The pattern mask layer includes at least one opening exposing a part of the gate material layer. An impurity treatment is performed to the gate material layer partially covered by the pattern mask layer for forming at least one doped region in the gate material layer. An etching process is performed to remove the gate material layer including the doped region. A dummy gate may be formed by patterning the gate material layer, and the impurity treatment may be performed after the step of forming the dummy gate. The performance of the etching processes for removing the gate material layer and/or the dummy gate may be enhanced, and the gate material residue issue may be solved accordingly.
    Type: Application
    Filed: August 30, 2016
    Publication date: March 1, 2018
    Inventors: Wen-Chien Hsieh, En-Chiuan Liou, Chih-Wei Yang, Yu-Cheng Tung, Po-Wen Su
  • Publication number: 20180053761
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate including at least one fin structure is provided. A gate material layer is formed on the semiconductor substrate, and the fin structure is covered by the gate material layer. A trench is formed partly in the gate material layer and partly in the fin structure. An isolation structure is formed partly in the trench and partly outside the trench. At least one gate structure is formed straddling the fin structure by patterning the gate material layer after the step of forming the isolation structure. A top surface of the isolation structure is higher than a top surface of the gate structure in a vertical direction for enhancing the isolation performance of the isolation structure. A sidewall spacer is formed on sidewalls of the isolation structure, and there is no gate structure formed on the isolation structure.
    Type: Application
    Filed: August 21, 2016
    Publication date: February 22, 2018
    Inventors: En-Chiuan Liou, Yu-Cheng Tung, Chih-Wei Yang
  • Publication number: 20180047635
    Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure, and a spacer. The semiconductor substrate includes at least one fin structure. The isolation structure is partly disposed in the fin structure and partly disposed above the fin structure. The fin structure includes a first fin and a second fin elongated in the same direction. A part of the isolation structure is disposed between the first fin and the second fin in the direction where the first fin and the second fin are elongated. The spacer is disposed on sidewalls of the isolation structure on the fin structure. The isolation structure in the present invention is partly disposed in the fin structure and partly disposed above the fin structure. The negative influence of a gate structure formed on the isolation structure and sinking into the isolation structure on the isolation performance of the isolation structure may be avoided accordingly.
    Type: Application
    Filed: September 13, 2016
    Publication date: February 15, 2018
    Inventors: En-Chiuan Liou, Yu-Cheng Tung, Chih-Wei Yang
  • Patent number: 9891781
    Abstract: A method of navigating between a plurality of different views of a home screen of a mobile communications device is provided. The mobile communications device includes a home button, a processor, and a display panel configured to cooperate with the processor to display one of the views of the home screen. The method includes selectively displaying one of the views of the home screen on the display panel based on a number of times the home button is activated within a predetermined time period. A non-transitory computer-readable medium and a mobile communications device of navigating between a plurality of different views of a home screen of a mobile communications device are also provided.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: February 13, 2018
    Assignee: HTC CORPORATION
    Inventors: Drew Bamford, David Brinda, Peter Chin, Jesse John Penico, Chih-Wei Yang, Huai-Ting Huang
  • Publication number: 20180040693
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a plurality of fin-shaped structures and a first shallow trench isolation (STI) around the fin-shaped structures on the first region and the second region; forming a patterned hard mask on the second region; removing the fin-shaped structures and the first STI from the first region; forming a second STI on the first region; removing the patterned hard mask; and forming a gate structure on the second STI.
    Type: Application
    Filed: October 18, 2017
    Publication date: February 8, 2018
    Inventors: En-Chiuan Liou, Chih-Wei Yang, Yu-Cheng Tung, Chun-Yuan Wu
  • Patent number: 9875937
    Abstract: The present invention provides a method for forming a semiconductor structure. Firstly, a substrate is provided, the substrate comprises an insulating layer and at least one first nano channel structure disposed thereon, a first region and a second region being defined on the substrate, next, a hard mask is formed within the first region, afterwards, an etching process is performed, to remove parts of the insulating layer within the second region, an epitaxial process is then performed, to form an epitaxial layer on the first nano channel structure, and an anneal process is performed, to transform the first nano channel structure and the epitaxial layer into a first nanowire structure, wherein the diameter of the first nanowire structure within the first region is different from the diameter of the first nanowire structure within the second region.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: January 23, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung, Chih-Wei Yang
  • Patent number: 9875928
    Abstract: A method for fabricating metal interconnect structure is disclosed. The method includes the steps of: providing a substrate having a first inter-metal dielectric (IMD) layer thereon; forming a metal interconnection in the first IMD layer; removing part of the first IMD layer; forming a spacer adjacent to the metal interconnection; and using the spacer as mask to remove part of the first IMD layer for forming an opening in the first IMD layer.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: January 23, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung, Chih-Wei Yang
  • Publication number: 20170347505
    Abstract: An inserting device includes a feeding mechanism, a positioning mechanism, and an assembling mechanism. The feeding mechanism includes a first supporting plate, a second supporting plate, a lifting assembly and a single-axis sliding table. The second supporting plate includes a first place position and an adjacent second place position. The second supporting plate and the first supporting plate can form a receiving space. The lifting assembly lifts trays located on the first place position and the second place position. The single-axis sliding table is received in the receiving space. The single-axis sliding table includes a sliding block. The sliding block receives the tray dropped from the first placing position and further carries the tray away from the first placing position. The positioning mechanism includes a clamping jaw. The clamping jaw clamps a workpiece from the tray and positions the workpiece again. The assembling mechanism assemblies the workpiece on a product.
    Type: Application
    Filed: July 8, 2016
    Publication date: November 30, 2017
    Inventors: JIAN-DE ZHANG, CHIH-WEI YANG, BAI-TONG FU, TSAI-SHENG LAN
  • Publication number: 20170309520
    Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a first metal gate and a second metal gate are formed on the substrate, in which the first metal gate includes a first work function metal layer, the second metal gate includes a second work function metal layer, the first metal gate and the second metal gate include different size, and the first work function metal layer and the second work function metal layer include different thickness.
    Type: Application
    Filed: May 19, 2016
    Publication date: October 26, 2017
    Inventors: En-Chiuan Liou, Chih-Wei Yang, Kuan-Ying Lai
  • Patent number: 9777743
    Abstract: A centrifugal fan impeller structure includes a hub and a blade body set. The hub has an extension section. The blade body set has multiple blade bodies. The blade bodies outward extend from the extension section of the hub. Each two adjacent blade bodies define therebetween a flow way, an air outlet and an air inlet. The air outlet and the air inlet are respectively positioned at two ends of the flow way in communication with the flow way. The air outlets are arranged at unequal intervals so as to greatly reduce noise in operation.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: October 3, 2017
    Assignee: Asia Vital Components Co., Ltd.
    Inventors: Chih-Wei Yang, Sheng-Pei Lee
  • Patent number: 9777742
    Abstract: A centrifugal fan impeller structure includes a hub having multiple blades. The blades extend from a circumference of the hub in a direction away from the hub. Each two adjacent blades define therebetween a flow way, an air outlet and an air inlet. The air outlet and the air inlet are respectively positioned at two ends of the flow way in communication with the flow way. The air outlets are arranged at unequal intervals so as to greatly reduce noise in operation.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: October 3, 2017
    Assignee: Asia Vital Components Co., Ltd.
    Inventors: Chih-Wei Yang, Sheng-Pei Lee
  • Patent number: 9754841
    Abstract: The present invention provides a method of forming an integrated circuit including a substrate, a first transistor, a second transistor and a third transistor. The first transistor has a first metal gate including a first bottom barrier layer, a first work function metal layer and a first metal layer. The second transistor has a second metal gate including a second bottom barrier layer, a second work function metal layer and a second metal layer. The third transistor has a third metal gate including a third bottom barrier layer, a third work function metal layer and a third metal layer. The first transistor, the second transistor and the third transistor has the same conductive type. A nitrogen concentration of the first bottom barrier layer>a nitrogen concentration of the second bottom barrier layer>a nitrogen concentration of the third bottom barrier layer.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: September 5, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Wei Yang, Yu-Feng Liu, Jian-Cun Ke, Chia-Fu Hsu, Yu-Ru Yang, En-Chiuan Liou
  • Publication number: 20170235696
    Abstract: An apparatus may include a chassis that can receive a sled and a locking mechanism. The locking mechanism can mechanically lock the sled to the chassis to prevent a sudden power loss that can be caused from an unexpected removal of the sled from the chassis. To avoid a sudden power loss, a voltage-sensing electrical switch lock can be implemented to the chassis to mechanically lock the sled to the chassis until the sled is ready to be removed. The sled may include one or more computing devices that need to be inactive before removing the sled. The apparatus includes a controller that may detect whether at least one of computing devices in the sled are in an active state or in an inactive state. Based on the determination of the state of the computing devices in the sled, the controller may activate the locking mechanism or de-active locking mechanism.
    Type: Application
    Filed: February 17, 2016
    Publication date: August 17, 2017
    Inventors: Jen-Hsuen HUANG, Fa-Da LIN, Chih-Wei YU, Chih-Wei YANG
  • Patent number: 9688303
    Abstract: A system and method for detecting failure of a steering angle sensor include: a steering angle sensor, an angular position encoder and an electronic control unit. The electronic control unit reads an initial value of the steering wheel rotation angle signal and estimates a rotation angle of a steering wheel based on the motor rotation angle signal, the electronic control unit checks if a difference between an actual value of the steering wheel rotation angle signal and an estimated rotation angle of the steering wheel is smaller than a predetermined value or not, if the difference is bigger than the predetermined value, it means that the steering wheel rotation angle signal fails, and the estimated rotation angle of the steering wheel serves as a substitute signal and is sent to the electronic control unit.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: June 27, 2017
    Assignee: Hiwin Technologies Corp.
    Inventor: Chih-Wei Yang
  • Patent number: 9660022
    Abstract: A method of fabricating a single diffusion break includes providing a fin with two gate structures crossing the fin and a middle dummy gate structure crossing the fin, wherein the middle dummy gate structure is sandwiched by the gate structures. Later, numerous spacers are formed and each spacer respectively surrounds the gate structures and the middle dummy gate structure. Then, the middle dummy gate structure, and part of the fin directly under the middle dummy gate structure are removed to form a recess. Finally, an isolating layer in the recess is formed to close an entrance of the recess so as to form a void embedded within the recess.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: May 23, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Chih-Wei Yang, Yu-Cheng Tung, Chia-Hsun Tseng
  • Publication number: 20170117151
    Abstract: An integrated circuit process includes the following steps. A substrate including a first area and a second area is provided. A plurality of line patterns cover the substrate of the first area, and a sacrificial line pattern covers the substrate of the second area, wherein these line patterns separate from and are orthogonal to the sacrificial line pattern. The present invention also provides an integrated circuit formed by said process. A substrate includes a first area and a second area; a plurality of line patterns cover the substrate of the first area; a slot pattern is in the substrate of the second area, wherein these line patterns are orthogonal to the slot pattern. Additionally, a plurality of line patterns cover the substrate; a sacrificial line pattern is at ends of the line patterns, wherein these line patterns separate from and are orthogonal to the sacrificial line pattern.
    Type: Application
    Filed: November 19, 2015
    Publication date: April 27, 2017
    Inventors: En-Chiuan Liou, Chih-Wei Yang, Kuei-Chun Hung