Abstract: The present disclosure relates to an integrated circuit, which includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a lower metal layer, an intermediate metal layer disposed over the lower metal layer, and an upper metal layer disposed over the intermediate metal layer. An upper surface of the lower metal layer and a lower surface of the intermediate metal layer are spaced vertically apart by a first distance. A resistive random access memory (RRAM) cell is arranged between the lower metal layer and the upper metal layer. The RRAM cell includes a bottom electrode and a top electrode which are separated by a data storage layer having a variable resistance. The data storage layer vertically spans a second distance that is greater than the first distance.

Abstract: A method includes forming a protection material over a conductive structure, an opening over the structure is partially filled with a first electrode material to form a first electrode; a resistance variable layer and a second electrode material are also formed in the opening. The second electrode material and the resistance variable layer are patterned to form a memory element. The method includes forming an interlayer dielectric over the memory element and the periphery region of the substrate and disposing contacts in the interlayer dielectric.

Abstract: The present disclosure relates to a resistive random access memory (RRAM) device. The RRAM device has a bottom electrode arranged over a bottom electrode via. A variable resistive dielectric layer is arranged over the bottom electrode. The variable resistive dielectric layer extends to within a recess in an upper surface of the bottom electrode. A top electrode is disposed over the variable resistive dielectric layer. A top electrode via extends outward from an upper surface of the top electrode at a position centered along a first axis that is laterally offset from a second axis centered upon the recess within the upper surface of the bottom electrode.

Abstract: In some embodiments, the present disclosure relates to a method of operating an RRAM cell having a PMOS access transistor. The method may be performed by forming an initial conductive filament within a dielectric data storage layer of an RRAM cell having a bottom electrode connected to a drain terminal of a PMOS transistor and a top electrode separated from the bottom electrode by the dielectric data storage layer. The initial conductive filament is formed by turning on the PMOS transistor by providing a substantially zero first forming voltage to a gate terminal of the PMOS transistor, by providing a substantially zero second forming voltage to a source terminal of the PMOS transistor, by providing a first non-zero forming voltage to a bulk terminal of the PMOS transistor, and by providing a second non-zero forming voltage to the top electrode.

Abstract: Some embodiments relate to an integrated circuit including a memory cell. The integrated circuit includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a plurality of dielectric layers and a plurality of metal layers that are stacked over one another in alternating fashion. The plurality of metal layers include a lower metal layer and an upper metal layer disposed over the lower metal layer. A bottom electrode is disposed over and in electrical contact with the lower metal layer. A data storage layer is disposed over an upper surface of bottom electrode. A top electrode is disposed over an upper surface of the data storage layer and is in direct electrical contact with a lower surface of the upper metal layer.

Abstract: A method includes applying a first voltage setting to a memory cell for a first period of time in response to a command for programming a first logical state to the memory cell, obtaining a first stored logical state of the memory cell after the applying the first voltage setting operation, and if the first stored logical state differs from the first logical state, applying a second voltage setting to the memory cell.

Abstract: A memory cell and method including a first electrode formed through a first opening in a first dielectric layer, a resistive layer formed on the first electrode, a spacing layer formed on the resistive layer, a second electrode formed on the resistive layer, and a second dielectric layer formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the first opening. The spacing layer extends from the second distance to the first distance. The second electrode is coupled to a second metal layer using a via that extends through the second opening.

Abstract: The present disclosure relates to an integrated chip comprising an RRAM cell that is driven by a PMOS transistor, and an associated method of formation. In some embodiments, the integrated chip has a PMOS transistor arranged within a semiconductor substrate. A resistive RRAM cell is arranged within an inter-level dielectric (ILD) layer overlying the semiconductor substrate. The RRAM cell has a first conductive electrode separated from a second conductive electrode by a dielectric data storage layer having a variable resistance. The first conductive electrode is connected to a drain terminal of the PMOS transistor by one or more metal interconnect layers. The use of a PMOS transistor to drive the RRAM cell allows for impact of the body effect to be reduced and therefore allows for a reset operation to be performed at a low power and in a short amount of time.

Abstract: A resistive random access memory (RRAM) structure includes a resistive memory element formed on a semiconductor substrate and designed for data storage. The resistive element includes a resistive material layer. The resistive element further includes first and second electrodes interposed by the resistive material layer. The resistive element further includes a field effect transistor (FET) formed on the semiconductor substrate and coupled with the resistive memory element, wherein the FET includes asymmetric source and drain, the drain having a higher doping concentration than the source. The resistive memory element is coupled with the drain.

Abstract: The present disclosure relates to an integrated circuit, which includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a lower metal layer, an intermediate metal layer disposed over the lower metal layer, and an upper metal layer disposed over the intermediate metal layer. An upper surface of the lower metal layer and a lower surface of the intermediate metal layer are spaced vertically apart by a first distance. A resistive random access memory (RRAM) cell is arranged between the lower metal layer and the upper metal layer. The RRAM cell includes a bottom electrode and a top electrode which are separated by a data storage layer having a variable resistance. The data storage layer vertically spans a second distance that is greater than the first distance.

Abstract: A memory cell and method including a first electrode formed through a first opening in a first dielectric layer, a resistive layer formed on the first electrode, a spacing layer formed on the resistive layer, a second electrode formed on the resistive layer, and a second dielectric layer formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the first opening. The spacing layer extends from the second distance to the first distance. The second electrode is coupled to a second metal layer using a via that extends through the second opening.

Abstract: Some embodiments relate to an integrated circuit device. The integrated circuit device includes a resistive random access memory (RRAM) cell, which includes a top electrode and a bottom electrode that are separated by a RRAM dielectric layer. The top electrode of the RRAM cell has a recess in its upper surface. A via is disposed over the RRAM cell and contacts the top electrode within the recess.

Abstract: The present disclosure provides one embodiment of a resistive random access memory (RRAM) structure. The RRAM structure includes a resistive memory element formed on a semiconductor substrate and designed for data storage; and a field effect transistor (FET) formed on the semiconductor substrate and coupled with the resistive memory element. The FET includes asymmetric source and drain. The resistive element includes a resistive material layer and further includes first and second electrodes interposed by the resistive material layer.

Abstract: The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a non-planar portion, a resistive material layer conformally covering the non-planar portion of the bottom electrode; and, a top electrode on the resistive material layer. The via portion of the bottom electrode is embedded in a first RRAM stop layer. The non-planar portion of the bottom electrode has an apex and is centered above the via portion.

Abstract: A resistive random access memory (RRAM) cell comprises a transistor having a gate and a source/drain region, a bottom electrode coplanar with the gate, a resistive material layer over the bottom electrode, a top electrode over the resistive material layer, and a conductive material electrically connecting the bottom electrode to the source/drain region.

Abstract: A semiconductor structure includes a memory region. A memory structure is disposed on the memory region. The memory structure includes a first electrode, a resistance variable layer, protection spacers and a second electrode. The first electrode has a top surface and a first outer sidewall surface on the memory region. The resistance variable layer has a first portion and a second portion. The first portion is disposed over the top surface of the first electrode and the second portion extends upwardly from the first portion. The protection spacers are disposed over a portion of the top surface of the first electrode and surround the second portion of the resistance variable layer. The protection spacers are configurable to protect at least one conductive path in the resistance variable layer. The protection spacers have a second outer sidewall surface substantially aligned with the first outer sidewall surface of the first electrode.

Abstract: A method of forming a magnetoresistive random access memory (MRAM) device including a perpendicular MTJ (magnetic tunnel junction) is provided. The method includes forming a magnetic tunneling junction (MTJ) over a bottom electrode layer. A top electrode layer is formed over an upper surface of the MTJ, and a hard mask is formed over an upper surface of the top electrode layer. A first etch is performed through the top electrode layer, through regions of the MTJ unmasked by the hard mask, to form a top electrode and an etched MTJ. Sidewall spacers are formed extending from an upper surface of the hard mask or the top electrode, along sidewalls of the top electrode and the etched MTJ, to a point below or about even with an upper surface of the bottom electrode. A resulting MRAM device structure is also provided.

Abstract: Some embodiments relate to an integrated circuit device. The integrated circuit device includes a resistive random access memory (RRAM) cell, which includes a top electrode and a bottom electrode that are separated by a RRAM dielectric layer. The top electrode of the RRAM cell has a recess in its upper surface. A via is disposed over the RRAM cell and contacts the top electrode within the recess.

Abstract: The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure electrically connected to the transistor. The RRAM structure includes a bottom electrode having a via portion and a top portion, a resistive material layer over the bottom electrode and having a same width as the top portion of the bottom electrode, and a top electrode over the resistive material layer and having a smaller width than the resistive material layer.

Abstract: The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a top portion, a resistive material layer on the bottom electrode having a width that is same as a width of the top portion of the bottom electrode; a capping layer over the bottom electrode; a spacer surrounding the capping layer; and, a top electrode on the capping layer having a smaller width than the resistive material layer. The RRAM cell further includes a conductive material connecting the top electrode of the RRAM structure to a metal layer.