Patents by Inventor Chih Yeh

Chih Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240128211
    Abstract: Some implementations described herein provide techniques and apparatuses for a stacked semiconductor die package. The stacked semiconductor die package may include an upper semiconductor die package above a lower semiconductor die package. The stacked semiconductor die package includes one or more rows of pad structures located within a footprint of a semiconductor die of the lower semiconductor die package. The one or more rows of pad structures may be used to mount the upper semiconductor die package above the lower semiconductor die package. Relative to another stacked semiconductor die package including a row of dummy connection structures adjacent to the semiconductor die that may be used to mount the upper semiconductor die package, a size of the stacked semiconductor die package may be reduced.
    Type: Application
    Filed: April 27, 2023
    Publication date: April 18, 2024
    Inventors: Chih-Wei WU, An-Jhih SU, Hua-Wei TSENG, Ying-Ching SHIH, Wen-Chih CHIOU, Chun-Wei CHEN, Ming Shih YEH, Wei-Cheng WU, Der-Chyang YEH
  • Patent number: 11961800
    Abstract: A method for forming a via in a semiconductor device and a semiconductor device including the via are disclosed. In an embodiment, the method may include bonding a first terminal and a second terminal of a first substrate to a third terminal and a fourth terminal of a second substrate; separating the first substrate to form a first component device and a second component device; forming a gap fill material over the first component device, the second component device, and the second substrate; forming a conductive via extending from a top surface of the gap fill material to a fifth terminal of the second substrate; and forming a top terminal over a top surface of the first component device, the top terminal connecting the first component device to the fifth terminal of the second substrate through the conductive via.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Wen-Chih Chiou, Tsang-Jiuh Wu, Der-Chyang Yeh, Ming Shih Yeh
  • Publication number: 20240120334
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming an isolation layer over a substrate. The method includes forming a spacer layer over the first fin, the second fin, and the isolation layer. The method includes forming a gate dielectric layer in the first trench and covering the first fin, the second fin, and the isolation layer exposed by the first trench. The method includes partially removing the gate dielectric layer to form a second trench in the gate dielectric layer and between the first fin and the second fin. The method includes forming a gate electrode in the first trench of the spacer layer and over the gate dielectric layer.
    Type: Application
    Filed: February 9, 2023
    Publication date: April 11, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Chih KAO, Hsin-Che CHIANG, Jeng-Ya YEH
  • Patent number: 11956462
    Abstract: Video processing methods and apparatuses for coding a current block comprise receiving input data of a current block, partitioning the current block into multiple sub-blocks, deriving sub-block MVs for the current block according to a sub-block motion compensation coding tool, constraining the sub-block MVs to form constrained sub-block MVs, and encoding or decoding the current block using the constrained sub-block MVs, and applying motion compensation to the current block using the constrained sub-block MVs to encode or decode the current block. The sub-block MVs may be constrained according to a size, width, or height of the current block or a sub-block, an inter prediction direction of one of control point MVs of the current block, the current block, or current sub-block, the control point MVs, or a combination of the above.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: April 9, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Tzu-Der Chuang, Ching-Yeh Chen, Chen-Yen Lai, Chih-Wei Hsu
  • Patent number: 11956421
    Abstract: Method and apparatus of video coding are disclosed. According to one method, in the decoder side, a predefined Intra mode is assigned to a neighboring block adjacent to the current luma block when the neighboring block satisfies one or more conditions. An MPM (Most Probable Mode) list is derived based on information comprising at least one of neighboring Intra modes. A current Intra mode is derived utilizing the MPM list. The current luma block is decoded according to the current Intra mode According to another method, a predefined Intra mode is assigned to a neighboring block adjacent to the current luma block if the neighboring block is coded in BDPCM (Block-based Delta Pulse Code Modulation) mode, where the predefined Intra mode is set to horizontal mode or vertical mode depending on prediction direction used by the BDPCM mode.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: April 9, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Man-Shu Chiang, Chih-Wei Hsu, Tzu-Der Chuang, Ching-Yeh Chen, Yu-Wen Huang, Shih-Ta Hsiang
  • Patent number: 11956469
    Abstract: Video processing methods and apparatuses implemented in a video encoding or decoding system with conditional secondary transform signaling. The video encoding system determines and applies a transform operation to residuals of a transform block to generate final transform coefficients, and adaptively signals a secondary transform index according to a position of a last significant coefficient in the transform block. A value of the secondary transform index is determined according to the transform operation.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: April 9, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Man-Shu Chiang, Chih-Wei Hsu, Tzu-Der Chuang, Ching-Yeh Chen
  • Publication number: 20240113036
    Abstract: An electromagnetic interference (EMI) shielding package structure, a manufacturing method thereof, and an electronic assembly are provided. The EMI shielding package structure includes a carrier, at least one chip mounted on a first board surface of the carrier, an encapsulant formed on the carrier and packaging the at least one chip, an EMI shielding layer formed on an outer surface of the encapsulant, and an insulating layer. The insulating layer includes a spraying portion and a capillary permeating portion. The spraying portion is formed at least part of an outer surface of the EMI shielding layer. The capillary permeating portion is formed by extending from a bottom end of the spraying portion toward a second board surface of the carrier through capillarity, and the capillary permeating portion covers a bottom edge of the EMI shielding layer.
    Type: Application
    Filed: November 17, 2022
    Publication date: April 4, 2024
    Inventors: CHIH-HAO LIAO, SHU-HAN WU, HSIN-YEH HUANG
  • Patent number: 11943476
    Abstract: Video processing methods and apparatuses implemented in a video encoding or decoding system with conditional secondary transform signaling. The video encoding system determines and applies a transform operation to residuals of one or more transform blocks to generate final transform coefficients, and skip signaling a secondary transform index if a position of a last significant coefficient in each considered transform block is less than or equal to a predefined position; otherwise, the video encoding system signals a secondary transform index according to the transform operation.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: March 26, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Man-Shu Chiang, Chih-Wei Hsu, Tzu-Der Chuang, Ching-Yeh Chen
  • Patent number: 11941338
    Abstract: Integrated circuits (IC) are provided. An IC includes a plurality of macros and a top channel. Each macro includes a macro boundary and a main pattern surrounded by the macro boundary. The top channel includes a plurality of first and second sub-channels. Each first sub-channel is arranged between a first macro and a second macro, and is formed by a plurality of first dummy boundary cells. Each second sub-channel is arranged between two of the second macros, and is formed by a plurality of second dummy boundary cells. The macro boundaries of the first macros are formed by the first dummy boundary cells, and the macro boundaries of the second macros are formed by the second dummy boundary cells. A first gate length of dummy patterns within the first dummy boundary cells is greater than a second gate length of dummy patterns within the second dummy boundary cells.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yi Hu, Chih-Ming Chao, Chi-Yeh Yu
  • Publication number: 20240096822
    Abstract: A package structure is provided. The package structure includes a first conductive pad in a first insulating layer, a conductive via in a second insulating layer directly under the first conductive pad, and a first under bump metallurgy structure directly under the first conductive via. In a first horizontal direction, the conductive via is narrower than the first under bump metallurgy structure, and the first under bump metallurgy structure is narrower than the first conductive pad.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Chia-Kuei HSU, Ming-Chih YEW, Shu-Shen YEH, Che-Chia YANG, Po-Yao LIN, Shin-Puu JENG
  • Publication number: 20240087933
    Abstract: A wafer transporting method includes following operations. A plurality of wafers are received in a semiconductor container attached to a mobile vehicle. An air processing system is coupled to a wall of the semiconductor container. The air processing system includes an inlet valve, an outlet valve, a pump between the inlet valve and the outlet valve, and a desiccant coupled to the pump. The semiconductor container is moved. The pump of the air processing system is turned on to extract air from inside the semiconductor container into the air processing system through the inlet valve. Humidity of the air is reduced when the air passes through the desiccant of the air processing system. The air is returned back to the semiconductor container through the outlet valve.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Inventors: YOU-CHENG YEH, MAO-CHIH HUANG, YEN-CHING HUANG, YU HSUAN CHUANG, TAI-HSIANG LIN, JIAN-SHIAN LIN
  • Publication number: 20240088095
    Abstract: A method for forming a chip package structure. The method includes bonding first connectors over a front surface of a semiconductor wafer. The method also includes dicing the semiconductor wafer from a rear surface of the semiconductor wafer to form semiconductor dies and mounting first and second semiconductor dies in the semiconductor dies over a top surface of the interposer substrate. The method further forming an encapsulating layer over the top surface of the interposer substrate to cover the first semiconductor die and the second semiconductor die. A first sidewall of the first semiconductor die faces a second sidewall of the second semiconductor die, and upper portions of the first sidewall and the second sidewall have a tapered contour, to define a top die-to-die distance and a bottom die-to-die distance that is less than the top die-to-die distance.
    Type: Application
    Filed: November 24, 2023
    Publication date: March 14, 2024
    Inventors: Chin-Hua WANG, Shin-Puu JENG, Po-Yao LIN, Po-Chen LAI, Shu-Shen YEH, Ming-Chih YEW, Yu-Sheng LIN
  • Patent number: 11930174
    Abstract: A method and apparatus for block partition are disclosed. If a cross-colour component prediction mode is allowed, the luma block and the chroma block are partitioned into one or more luma leaf blocks and chroma leaf blocks. If a cross-colour component prediction mode is allowed, whether to enable an LM (Linear Model) mode for a target chroma leaf block is determined based on a first split type applied to an ancestor chroma node of the target chroma leaf block and a second split type applied to a corresponding ancestor luma node. According to another method, after the luma block and the chroma block are partitioned using different partition tress, determine whether one or more exception conditions to allow an LM for a target chroma leaf block are satisfied when the chroma partition tree uses a different split type, a different partition direction, or both from the luma partition tree.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: March 12, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Chia-Ming Tsai, Tzu-Der Chuang, Chih-Wei Hsu, Ching-Yeh Chen, Zhi-Yi Lin
  • Patent number: 11926266
    Abstract: An installing module includes a seat bracket, a plurality of lower gaskets, a device bracket and an upper gasket. The seat bracket includes a first locking plate and a second locking plate locked to each other. The first locking plate includes a first concave and the second locking plate includes a second concave corresponding to the first concave. The lower gaskets are respectively disposed on the first concave and the second concave. The lower gaskets face each other and jointly define a lower assembly hole and are disposed on a lower side of a head-support fixer of a car seat. The device bracket is locked to the seat bracket and an electronic device is pivotally coupled to the device bracket. The upper gasket is disposed between the device bracket and the head-support fixer, and the head-support fixer is clamped between the upper gasket and the lower gaskets.
    Type: Grant
    Filed: August 26, 2022
    Date of Patent: March 12, 2024
    Assignee: PEGATRON CORPORATION
    Inventors: Shih-Wei Yeh, Chien-Chih Lin, Yi-Ming Chou, Chun-Chieh Chang
  • Publication number: 20240080490
    Abstract: A video codec receives data for a block of pixels to be encoded or decoded as a current block of a current picture of a video. The video codec signals or parses a first syntax element for a first coding mode in a particular set of two or more coding modes. Each of coding mode of the particular set of coding modes modifies a merge candidate or an inter-prediction that is generated based on the merge candidate. The video codec enables the first coding mode and disables one or more other coding modes in the particular set of coding modes. The disabled one or more coding modes in the particular set of coding modes are disabled without parsing syntax elements for the disabled coding modes. The video codec encodes or decodes the current block by using the enabled first coding mode and bypassing the disabled coding modes.
    Type: Application
    Filed: November 10, 2023
    Publication date: March 7, 2024
    Applicant: HFI Innovation Inc.
    Inventors: Man-Shu Chiang, Chih-Wei Hsu, Ching-Yeh Chen
  • Publication number: 20240079010
    Abstract: A method of controlling a battery-powered remote controller to decrease a duty cycle to allow continued operations despite the quantity of the battery is bad. The method determines a drop in voltage of the battery in standby mode as voltage of the battery is being read. When receiving a command to activate a voice function, determining whether the drop in voltage in the standby mode is greater than or equal to a preset value. If the drop is greater than or equal to the preset value, the method then determines whether the drop in voltage falls in a preset range. If the drop falls in the preset range, the method regulates a duty cycle of the pulse signal activating the voice function, and activates the voice function as required. A remote controller and a non-transitory storage medium are also provided.
    Type: Application
    Filed: November 10, 2023
    Publication date: March 7, 2024
    Inventors: HUANG-YU CHIANG, Chung-Chih Yeh
  • Patent number: 11924444
    Abstract: Method and apparatus for constrained de-blocking filter are disclosed. One method receives input data related to a current block in a current picture at a video encoder side or a video bitstream corresponding to compressed data including the current block in the current picture at a video decoder side, and determines a first boundary associated with the current block, wherein the first boundary corresponds to one vertical boundary or one horizontal boundary of the current block. The method then applies de-blocking process to a reconstructed current block corresponding to the current block to result in a filtered-reconstructed current block, using a plurality of first reference samples at a same side of the first boundary, and replaces a first set of the first reference samples by one or more padding values. The method then generates a filtered decoded picture including the filtered-reconstructed current block.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: March 5, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Chia-Ming Tsai, Chih-Wei Hsu, Ching-Yeh Chen, Tzu-Der Chuang, Yu-Wen Huang
  • Patent number: 11920190
    Abstract: Methods of amplifying and determining a target nucleotide sequence are provided. The method of amplifying the target nucleotide sequence includes the following steps. A first adaptor and a second adaptor are linked to two ends of a double-stranded nucleic acid molecule with a target nucleotide sequence respectively to form a nucleic acid template, in which the first adaptor includes a Y-form adaptor or a hairpin adaptor and the second adaptor is a hairpin adaptor. Then, a PCR amplification cycle is performed on the nucleic acid template to obtain a PCR amplicon of the target nucleotide sequence.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: March 5, 2024
    Assignee: Industrial Technology Research Institute
    Inventors: Pei-Shin Jiang, Jenn-Yeh Fann, Hung-Chi Chien, Yu-Yu Lin, Chih-Lung Lin
  • Patent number: 11917185
    Abstract: A method and apparatus of Inter prediction for video coding using Multi-hypothesis (MH) are disclosed. If an MH mode is used for the current block: at least one MH candidate is derived using reduced reference data by adjusting at least one coding-control setting; an Inter candidate list is generated, where the Inter candidate list comprises said at least one MH candidate; and current motion information associated with the current block is encoded using the Inter candidate list at the video encoder side or the current motion information associated with the current block is decoded at the video decoder side using the Merge candidate list. The coding control setting may correspond to prediction direction setting, filter tap setting, block size of reference block to be fetched, reference picture setting or motion limitation setting.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: February 27, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Man-Shu Chiang, Chih-Wei Hsu, Tzu-Der Chuang, Ching-Yeh Chen, Yu-Wen Huang
  • Publication number: 20240035971
    Abstract: A fluorescence lifetime imaging microscopy system comprises a microscope comprising an excitation source configured to direct an excitation energy to an imaging target, and a detector configured to measure emissions of energy from the imaging target, and a non-transitory computer-readable medium with instructions stored thereon, which perform steps comprising collecting a quantity of measured emissions of energy from the imaging target as measured data, providing a trained neural network configured to calculate fluorescent decay parameters from the quantity of measured emissions of energy, providing the data to the trained neural network, and calculating at least one fluorescence lifetime parameter with the neural network from the measured data, wherein the measured data comprises an input fluorescence decay histogram, and wherein the neural network was trained by a generative adversarial network. A method of training a neural network and a method of acquiring an image are also described.
    Type: Application
    Filed: September 17, 2021
    Publication date: February 1, 2024
    Inventors: Hsin-Chih Yeh, Yuan-I Chen, Yin-Jui Chang, Shih-Chu Liao, Trung Duc Nguyen, Soonwoo Hong, Yu-An Kuo, Hsin-Chin Li