Abstract: A method of controlling a battery-powered remote controller to decrease a duty cycle to allow continued operations despite the quantity of the battery is bad. The method determines a drop in voltage of the battery in standby mode as voltage of the battery is being read. When receiving a command to activate a voice function, determining whether the drop in voltage in the standby mode is greater than or equal to a preset value. If the drop is greater than or equal to the preset value, the method then determines whether the drop in voltage falls in a preset range. If the drop falls in the preset range, the method regulates a duty cycle of the pulse signal activating the voice function, and activates the voice function as required. A remote controller and a non-transitory storage medium are also provided.

Abstract: A SAR ADC includes: a sample-hold (S/H) circuit sampling an input voltage to generate a S/H output signal; a DAC generating a DAC output signal; a comparator comparing the DAC output signal with the S/H output signal to generate a comparison output signal; a SAR combinational digital circuit group; a multiplexer circuit; and a plurality of registers for registering the comparison output signal as register output signals and outputting as an output signal of the SAR ADC. The SAR combinational digital circuit group generates a plurality of first and second SAR output signals based on the register output signals. The multiplexer circuit is controlled by on the register output signals to select among the first and the second SAR output signals as a plurality of multiplexer output signals for sending to the DAC. A capacitor coupling relationship of the DAC is controlled by the multiplexer output signals.

Abstract: According to an aspect of the disclosure, the disclosure provides an ADC which includes not limited to: a DAC configured to generate a positive input delta voltage and a negative input delta voltage, a comparator electrically connected to the DAC and configured to receive the positive input delta voltage to generate a first digital output value and to receive the negative input delta voltage to generate a second digital output value, a logic circuit configured to receive, from the comparator, the first digital output value and the second digital output value to generate a digital quantization code according to half of a sum of the first digital output value and the second digital output value, and a calibration circuit configured to receive the digital quantization code from the logic circuit and calibrate an output of the ADC according to the digital quantization code to eliminate an offset error value.

Abstract: A first gate-all-around (GAA) transistor is formed on the first fin structure; the first GAA transistor has a channel region within a first plurality of nanostructures. A second GAA transistor is formed on the second fin structure; the second GAA transistor has a second channel region configuration. The second GAA transistor has a channel region within a second plurality of nanostructures. The second plurality of nanostructures is less than the first plurality of nanostructures.

Abstract: The invention relates to a method, a non-transitory computer-readable storage medium, and an apparatus for debugging a solid-state disk (SSD) device. The method is performed by a processing unit of a single-board personal computer (PC) to include: simulating to issue a first Joint Test Action Group (JTAG) command through a General-Purpose Input/Output (GPIO) interface (I/F) to the SSD device for stopping a running of a processing unit of a flash controller in the SSD device; simulating to issue a second JTAG command through the GPIO I/F to the SSD device for forcing the SSD device to exit a sleep mode; and simulating to issue a third JTAG command through the GPIO I/F to the SSD device for reading a designated length of data from a static random access memory (SRAM) in the SSD device.

Abstract: A SAR ADC includes: a sample-hold (S/H) circuit sampling an input voltage to generate a S/H output signal; a DAC generating a DAC output signal; a comparator comparing the DAC output signal with the S/H output signal to generate a comparison output signal; a SAR combinational digital circuit group; a multiplexer circuit; and a plurality of registers for registering the comparison output signal as register output signals and outputting as an output signal of the SAR ADC. The SAR combinational digital circuit group generates a plurality of first and second SAR output signals based on the register output signals. The multiplexer circuit is controlled by on the register output signals to select among the first and the second SAR output signals as a plurality of multiplexer output signals for sending to the DAC. A capacitor coupling relationship of the DAC is controlled by the multiplexer output signals.

Abstract: The invention provides a chemical-mechanical polishing composition comprising (a) abrasive particles, b) a removal rate inhibitor selected from (I) a surfactant comprising a polyoxyalkylene functional group and a sulfonate functional group, (II) a surfactant comprising a polyoxyalkylene functional group and a sulfate functional group, (III) a first surfactant comprising a polyoxyalkylene functional group and a second surfactant comprising a sulfonate functional group, and (IV) a first surfactant comprising a polyoxyalkylene functional group and a second surfactant comprising a sulfate functional group, and (c) an aqueous carrier. The invention also provides a method of chemically-mechanically polishing a substrate comprising TiN and SiN with the inventive chemical-mechanical polishing composition.

Abstract: A method of controlling a battery-powered remote controller to decrease a duty cycle to allow continued operations despite the quantity of the battery is bad. The method determines a drop in voltage of the battery in standby mode as voltage of the battery is being read. When receiving a command to activate a voice function, determining whether the drop in voltage in the standby mode is greater than or equal to a preset value. If the drop is greater than or equal to the preset value, the method then determines whether the drop in voltage falls in a preset range. If the drop falls in the preset range, the method regulates a duty cycle of the pulse signal activating the voice function, and activates the voice function as required. A remote controller and a non-transitory storage medium are also provided.

Abstract: A fluorescence lifetime imaging microscopy system comprises a microscope comprising an excitation source configured to direct an excitation energy to an imaging target, and a detector configured to measure emissions of energy from the imaging target, and a non-transitory computer-readable medium with instructions stored thereon, which perform steps comprising collecting a quantity of measured emissions of energy from the imaging target as measured data, providing a trained neural network configured to calculate fluorescent decay parameters from the quantity of measured emissions of energy, providing the data to the trained neural network, and calculating at least one fluorescence lifetime parameter with the neural network from the measured data, wherein the measured data comprises an input fluorescence decay histogram, and wherein the neural network was trained by a generative adversarial network. A method of training a neural network and a method of acquiring an image are also described.

Abstract: A method of controlling a battery-powered remote controller to decrease a duty cycle to allow continued operations despite the quantity of the battery is bad determines a drop in voltage of the battery in standby mode as voltage of the battery is being read. When receiving a command to activate a voice function, determining whether the drop in voltage in standby mode is greater than or equal to a preset value. If yes, the method then determines whether the drop in voltage falls in a preset range. If yes, the method regulates a duty cycle of the pulse signal activating the voice function, and activates the voice function as required. A remote controller and a non-transitory storage medium are also provided.

Abstract: A memory comprising a memory array, including a plurality of blocks, and control circuits comprising logic to execute operations is provided. The operations include decoding a read setup burst command identifying (i) an address of a first read setup block in a set of read setup blocks and (ii) a number of read setup blocks, as candidates for read setup operations. The operations further including, in response to the decoding of the read setup burst command, performing a read setup burst operation on a plurality of read setup blocks of the set of read setup blocks.

Abstract: A storage device includes a memory array and a memory controller. The memory controller generates read and write commands for the memory array. An error correction code engine for the storage device is operable to use a plurality of different codeword sizes, different code rates, or different ECC algorithms. Logic is included that applies a selected codeword size, code rate or ECC algorithm in dependence on the operating conditions of the memory array.

Abstract: A storage device includes a memory array and a memory controller. The memory controller generates read and write commands for the memory array. An error correction code engine for the storage device is operable to use a plurality of different codeword sizes, different code rates, or different ECC algorithms. Logic is included that applies a selected codeword size, code rate or ECC algorithm in dependence on the operating conditions of the memory array.

Abstract: A method for detecting an abnormal occurrence of an application program includes a feature parameter collected according to the log data of at least one application program. The feature parameter is inputted into a first and a second prediction model and a first and a second detection model, and the feature parameter is calculated based on the first and the second prediction model and the first and the second detection model to respectively generate a first and a second prediction value and a first and a second detection value. The first and the second prediction value and the first and the second detection value are respectively weighted based on an abnormal score evaluation equation to generate an abnormal evaluation value of the application program. Finally, the abnormal evaluation value is inputted into a warning ranking model to rank the abnormal evaluation value, generating the corresponding warning signal.

Abstract: In some examples, an electronic device comprises a voltage supply circuit to provide a reference voltage usable to discharge pixels in a display device; and a scaler circuit coupled to the voltage supply circuit. The scaler circuit is to buffer first and second frames and dynamically control the voltage supply circuit to modify the reference voltage based on a frequency of the first frame differing from a frequency of the second frame.

Abstract: In some examples, an electronic device comprises a voltage supply circuit to provide a reference voltage usable to discharge pixels in a display device; and a scaler circuit coupled to the voltage supply circuit. The scaler circuit is to buffer first and second frames and dynamically control the voltage supply circuit to modify the reference voltage based on a frequency of the first frame differing from a frequency of the second frame.

Abstract: The invention relates to a method, a non-transitory computer-readable storage medium, and an apparatus for debugging a solid-state disk (SSD) device. The method is performed by a processing unit of a single-board personal computer (PC) to include: simulating to issue a first Joint Test Action Group (JTAG) command through a General-Purpose Input/Output (GPIO) interface (I/F) to the SSD device for stopping a running of a processing unit of a flash controller in the SSD device; simulating to issue a second JTAG command through the GPIO I/F to the SSD device for forcing the SSD device to exit a sleep mode; and simulating to issue a third JTAG command through the GPIO I/F to the SSD device for reading a designated length of data from a static random access memory (SRAM) in the SSD device.

Abstract: A memory comprising a memory array, including a plurality of blocks, and control circuits comprising logic to execute operations is provided. The operations include decoding a read setup burst command identifying (i) an address of a first read setup block in a set of read setup blocks and (ii) a number of read setup blocks, as candidates for read setup operations. The operations further including, in response to the decoding of the read setup burst command, performing a read setup burst operation on a plurality of read setup blocks of the set of read setup blocks.

Abstract: Methods include providing a first fin structure and a second fin structure each extending from a substrate. A first gate-all-around (GAA) transistor is formed on the first fin structure; the first GAA transistor has a channel region within a first plurality of nanostructures. A second GAA transistor is formed on the second fin structure; the second GAA transistor has a second channel region configuration. The second GAA transistor has a channel region within a second plurality of nanostructures. The second plurality of nanostructures is less than the first plurality of nanostructures.

Abstract: A method of operating a memory is provided. The method includes, in response to an access of a block of memory updating a first queue to identify the accessed block in response to a determination that the block is not already identified in the first queue and a determination that the block is not already identified in a second queue, and updating the second queue to identify the accessed block of memory in response to a determination that the block is already identified in the first queue. The method further includes scanning the second queue to identify, as a read setup candidate, each block of the memory that is identified as present in the second queue longer than a threshold, and performing a read setup operation on a block of memory that has been identified as the read setup candidate.