Abstract: A method for deployment scheduling for a mobile communication network is disclosed. The mobile network is to be changed from a first network plan to a second network plan, and both the first and second network plans include a plurality of BSC (base station controller) areas and location areas.

Abstract: A nonvolatile memory cell with a charge storage structure is read by measuring current (such as band-to-band current) between the substrate region of the memory cell and at least one of the current carrying nodes of the memory cell. To enhance the operation of the nonvolatile memory cell, the band structure engineering is used to alter the band structure between a bulk part of the device and another part of the device supporting the measurement current.

Abstract: A multi-Level Cell (MLC) can be used to store, for example, 4 bits per cell by storing two bits on each of two sides. Each side can store, e.g., four different current level states that can be determined by the number of holes injected into, e.g., nitride layer, during programming. As more holes are injected the current decreases for a given voltage. The current can be low, therefore, it can be advantageous in one embodiment to use a current amplifier. The current amplifier can be a BJT, MOS or other type of device.

Abstract: A string of memory cells with a charge trapping structure is read, by selecting part of a memory cell selected by a word line. Part of the memory cell is selected by turning on one of the pass transistors on either side of the string of memory cells. The charge storage state of the selected part is determined by measuring current in a bit line tied to both pass transistors.

Abstract: Methods and apparatuses for protecting charge trapping memory cells from over-erasing in response to an erase command are disclosed.

Abstract: An applying method for an adhesive according to an embodiment includes the following steps. First, gas is exhausted from a first exhaust pipe, so as to eliminate a part of the gas in a closed container. Next, the gas continues to be exhausted from the first exhaust pipe, so as to have the adhesive in the transmission pipeline become bubbled, and also to convey the bubbled adhesive to reach the supply vent. Later, gas is exhausted from the second exhaust pipe and continues to be exhausted from the first exhaust pipe, so as to greatly exhaust the gas in the closed container, and also to increase bubbling in the adhesive. Subsequently, the gas continues to be exhausted from the second exhaust pipe and ceases to be exhausted from the first exhaust pipe, so as to cause the adhesive to reach a gasified state. Also the gasified adhesive is supplied to the closed container from the supply vent, so that the gasified adhesive can adhere to and coat above the SiO2 layer.

Abstract: A network apparatus with secure IPSec mechanism and method for operating the same are disclosed. The network apparatus includes a VLAN, an MAC filter, an IP restriction unit and a static DHCP. The network apparatus provides physical separation between VPN and other untrustful network before a message is sent to an IPSec channel. Therefore, the IPSec channel can be securely accessed. The network apparatus is applicable for both household network and VPN.

Abstract: An array of memory cells with a charge trapping structure coupled in series is read, by measuring current that flows between the body region of the selected memory cell and the contact region of the selected memory cell. The charge storage state of the charge trapping structure affects the measured current.

Abstract: A method of reducing gate disturb in a charge-trapping layer memory cell by applying different Vpass voltages to different sides of a selected wordline. A higher Vpass voltage is used to pass higher source/drain voltage and a lower Vpass voltage is used to pass a lower source/drain voltage. By controlling the Vpass voltages on different sides of a selected wordline, it is possible to reduce a vertical field that is established in a gate region when the Vpass voltages are applied. A reduced vertical field results in suppressed gate disturb. The method also includes a novel bit-line biasing scheme that may further reduce the vertical field and thereby may further suppress gate disturb, particularly in an array of memory cells.

Abstract: A string of memory cells with a charge trapping structure coupled in series is read, by measuring current that flows between the body region of the selected memory cell and the contact region of the selected memory cell. The charge storage state of the charge trapping structure affects the measured current.

Abstract: A power supply apparatus is provided. When an electronic apparatus coupled to the power supply is in standby mode, a microprocessor delivers a standby control pulse. A feedback circuit receiving the standby control pulse directs a pulse width modulation (PWM) controller to deliver a periodic intermittent signal. A switching device of the power supply apparatus reduces its switching action to reduce switching power lost upon receipt of activated periodic intermittent signal.

Abstract: This invention relates to tetraphenylmethane-based oxadiazole molecules that act as electron transporting materials to be used in electroluminescent devices. The oxadiazole compounds are of the following formula. Each variable is defined in the specification.

Abstract: Methods and apparatuses for causing electroluminescence with charge trapping structures are disclosed. Various embodiments relate to methods and apparatuses for causing electroluminescence with charge carriers of one type provided to the charge trapping structure by a forward biased p-n structure or a reverse biased p-n structure.

Abstract: Programming nonvolatile memory cells is affected by the program disturb effect which causes data accuracy issues with nonvolatile memory. Rather than masking the voltage conditions that cause the program disturb effect, voltages are applied to neighboring nonvolatile memory cells, which takes advantage of the program disturb effect to program multiple cells quickly.

Abstract: A method for manufacturing an electrically programmable non-volatile memory cell comprises forming a first electrode on a substrate, forming an inter-electrode layer of material on the first electrode having a property which is characterized by progressive change in response to stress, and forming a second electrode over the inter-electrode layer of material. The inter-electrode layer comprises a dielectric layer, such as ultra-thin oxide, between the first and second electrodes. A programmable resistance, or other property, is established by stressing the dielectric layer, representing stored data. Embodiments of the memory cell are adapted to store multiple bits of data per cell and/or adapted for programming more than one time without an erase process.

Abstract: A memory cell with a charge trapping structure is operated by measuring current between the substrate region of the memory cell and at least one of the source region of the memory cell and the drain region of the memory cell. The read operation decreases the coupling between different parts of the charge trapping structure when other parts of the charge trapping structure store data that are not of interest. The sensing window of the memory cell can be greatly improved by this read operation. The memory cell is erased by increasing the net positive charge on the memory cell and programmed by increasing the net negative charge on the memory cell.

Abstract: A memory cell with a charge storage structure is read by measuring current between the substrate region of the memory cell and one of the current carrying nodes of the memory cell. The read operation decreases the coupling between different parts of the charge storage structure when other parts of the charge storage structure store data that are not of interest. The sensing window of the memory cell can be greatly improved by this read operation. Example arrangements are a single memory cell, a column or NOR-connected memory cells, and a virtual ground array of memory cells.

Abstract: A string of memory cells with a charge trapping structure is read, by selecting part of a memory cell selected by a word line. Part of the memory cell is selected by turning on one of the pass transistors on either side of the string of memory cells. The charge storage state of the selected part is determined by measuring current in a bit line tied to both pass transistors.

Abstract: A memory cell with a charge trapping structure is read by measuring current between the substrate region of the memory cell and one of the source region of the memory cell and the drain region of the memory cell. The read operation decreases the coupling between different parts of the charge trapping structure when other parts of the charge trapping structure store data that are not of interest. The sensing window of the memory cell can be greatly improved by this read operation.

Abstract: A memory cell with a charge storage structure is read by measuring current between the substrate region of the memory cell and one of the current carrying nodes of the memory cell. The read operation decreases the coupling between different parts of the charge storage structure when other parts of the charge storage structure store data that are not of interest. The sensing window of the memory cell can be greatly improved by this read operation. Example arrangements are a series of memory cells, and an array of series of memory cells.