Abstract: A process for fabricating a trench power semiconductor device is disclosed. A first dielectric layer between the pad oxide layer and the mask oxide layer is formed so as to form a gate with a height higher than the surface of the pad oxide layer after the first dielectric layer is removed. In addition, a sidewall structure is formed at laterals of the gate protruded from the surface of the trench structure. Hence the source structure and the first conductive layer formed at the surface of the gate can be isolated through the sidewall structure. When the trench power semiconductor device is processed at high frequency, the net resistance of the gate can be reduced by the first conductive layer, and thus the electrical properties thereof can be elevated.

Abstract: The present invention provides novel processes for the preparation of a cyclopentanone of Formula II and a lactone of Formula I, which are useful in the production of prostaglandins: wherein Z, R2, R3, X1, X2, and are as defined in the specification. The invention also provides novel enantiomerically enriched compounds.

Abstract: The present invention provides novel processes for the preparation of a cyclopentanone of Formula II and a lactone of Formula I, which are useful in the production of prostaglandins: wherein Z, R2, R3, X1, X2, and are as defined in the specification. The invention also provides novel enantiomerically enriched compounds.

Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract: A method of reducing gate disturb in a charge-trapping layer memory cell by applying different Vpass voltages to different sides of a selected wordline. A higher Vpass voltage is used to pass higher source/drain voltage and a lower Vpass voltage is used to pass a lower source/drain voltage. By controlling the Vpass voltages on different sides of a selected wordline, it is possible to reduce a vertical field that is established in a gate region when the Vpass voltages are applied. A reduced vertical field results in suppressed gate disturb. The method also includes a novel bit-line biasing scheme that may further reduce the vertical field and thereby may further suppress gate disturb, particularly in an array of memory cells.

Abstract: An etching apparatus is described, including an etching chamber, a gas pipe, a gas distribution plate and a heater. The gas pipe is disposed above the etching chamber for delivering a gas to the exterior surface of the etching chamber. The gas distribution plate is disposed at the outlet of the gas pipe, including a plate body and an inner collar-shaped part thereon facing the outlet of the gas pipe. The inner collar-shaped part and the portion of the plate body around the inner collar-shaped part each has multiple through holes therein. The heater is disposed around the space between the gas pipe and the etching chamber for heating the gas flowing out of the gas distribution plate.

Abstract: Methods and apparatuses for causing electroluminescence with charge trapping structures are disclosed. Various embodiments relate to methods and apparatuses for causing electroluminescence with charge carriers of one type provided to the charge trapping structure by a forward biased p-n structure or a reverse biased p-n structure.

Abstract: A PSM blank and method for forming a PSM using the PSM blank, the PSM blank including a light transmitting portion; an uppermost anti-reflection portion; a photosensitive layer stack on the anti-reflection portion comprising at least two photosensitive layers; wherein each photosensitive layer has a lower radiant energy exposure sensitivity compared to an underlying layer.

Abstract: Methods and apparatuses for protecting charge trapping memory cells from over-erasing in response to an erase command are disclosed.

Abstract: The present invention relates to novel processes for preparing optically active Cyclopentenones of Formula (R)-1, which are useful for the preparation of Prostaglandins and analogs thereof. The invention also relates to novel Cyclopentenones prepared from the processes.

Abstract: The present invention provides novel processes for the preparation of a cyclopentanone of Formula II and a lactone of Formula I, which are useful in the production of prostaglandins: wherein Z, R2, R3, X1, X2, and are as defined in the specification. The invention also provides novel enantiomerically enriched compounds.

Abstract: An array of charge trapping nonvolatile memory cells is arranged in several columns of cells, each arranged in a series, such as a NAND string. Each cell stores no more than a single charge storage state.

Abstract: An electrochemical testing device for a specimen includes a receiving member, an auxiliary electrode, a work module, a clamping module, and a reference electrode. The receiving member receives an electrolytic solution and includes a surrounding wall having a bottom open end. The auxiliary electrode is mounted in the receiving member. The work module holds the specimen and includes at least one upper plate covering the open end to close the receiving member and having an opening connected fluidly to an interior of the receiving member, a lower plate, a work electrode plate interposed between and contacting the upper and lower plates, and a test specimen holding site provided at the work electrode plate and connected fluidly to the opening. The clamping module clamps the work module against the surrounding wall. The reference electrode is disposed in the receiving member above the work electrode plate.

Abstract: An array of charge trapping nonvolatile memory cells is arranged in several columns of cells, each arranged in a series, such as a NAND string. Each cell stores no more than a single charge storage state.

Abstract: An etching apparatus is described, including an etching chamber, a gas pipe, a gas distribution plate and a heater. The gas pipe is disposed above the etching chamber for delivering a gas to the exterior surface of the etching chamber. The gas distribution plate is disposed at the outlet of the gas pipe, including a plate body and an inner collar-shaped part thereon facing the outlet of the gas pipe. The inner collar-shaped part and the portion of the plate body around the inner collar-shaped part each has multiple through holes therein. The heater is disposed around the space between the gas pipe and the etching chamber for heating the gas flowing out of the gas distribution plate.

Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract: A NAND type multi-bit charge storage memory array comprises a first and a second memory strings each of which includes one or more charge storage memory cells and two select transistors. The charge storage memory cells are connected in series to form a memory cell string. The two select transistors are connected in series to both ends of the memory cell string, respectively. The NAND type multi-bit charge storage memory array further comprises a shared bit line and a first and a second bit lines. The shared bit line is connected with the first ends of the first and the second memory strings. The first and the second bit lines are connected to the second ends of the first and the second memory strings, respectively. The first select transistor and the second select transistor of each memory string are controlled by a first and a second select transistor control lines, respectively.

Abstract: A method for manufacturing a multiple-gate memory cell which comprises a semiconductor body and a plurality of gates arranged in series and the semiconductor body includes first forming a plurality of gates spaced apart by about a gate width, forming an isolation layer on the sidewalls, and filling between the first plurality of gates to form a second plurality of gates. A charge storage structure is formed on the semiconductor body beneath each of all or some of the gates in the plurality of gates. Circuitry is formed to conduct source and drain bias voltages to the semiconductor body near a first gate and a last gate in the series, and circuitry to conduct gate bias voltages to the plurality of gates is included. The multiple-gate memory cell includes a continuous, multiple-gate channel region beneath the plurality of gates in the series, with charge storage locations between some or all of the gates.

Abstract: A memory architecture for an integrated circuit comprises a first memory array configured to store data for one pattern of data usage and a second memory array configured to store data for another pattern of data usage. The first and second memory arrays comprise charge storage based nonvolatile memory cells having substantially the same structure in both arrays. A first operation algorithm adapted for example for data flash applications is used for programming, erasing and reading data in the first memory array. A second operation algorithm adapted for example for code flash applications is used for programming, erasing and reading data in the second memory array, wherein the second operation algorithm is different than the first operation algorithm. Thus, one die with memory for both code flash and data flash applications can be easily manufactured using a simple process, at low cost and high yield.