Abstract: A memory cell with a charge storage structure is read by measuring current between the substrate region of the memory cell and one of the current carrying nodes of the memory cell. The read operation decreases the coupling between different parts of the charge storage structure when other parts of the charge storage structure store data that are not of interest. The sensing window of the memory cell can be greatly improved by this read operation. Example arrangements are a series of memory cells, and an array of series of memory cells.

Abstract: This invention relates to a method of preparing a compound of formula (I): The method includes reacting one or more compounds of formula (II): in the presence of a base and a halogenating agent. In formulas (I) and (II) above, each A, independently, is aryl or heteroaryl; each n, independently, is 0–3; and each R1, independently, is C1–C10 alkyl, C3–C20 cycloalkyl, C3–C20 heterocycloalkyl, aryl, heteroaryl, halo, cyano, nitro, ORa, NRaRb, SiRaRbRc, COORa, OC(O)Ra, C(O)NRaRb, N(Ra)—C(O)Rb, or SO3Ra; wherein each of Ra, Rb, and Rc, independently, is H, C1–C10 alkyl, C3–C20 cycloalkyl, C3–C20 heterocycloalkyl, aryl, or heteroaryl; thereby producing the compound of formula (I) in a one-pot reaction. This invention also relates to the compounds prepared by the method described above.

Abstract: This invention relates to a method of preparing a compound of formula (I): The method includes reacting one or more compounds of formula (II): in the presence of a base and a halogenating agent. In formulas (I) and (II) above, each A, independently, is aryl or heteroaryl; each n, independently, is 0-3; and each R1, independently, is C1-C10 alkyl, C3-C20 cycloalkyl, C3-C20 heterocycloalkyl, aryl, heteroaryl, halo, cyano, nitro, ORa, NRaRb, SiRaRbRc, COORa, OC(O)Ra, C(O)NRaRb, N(Ra)—C(O)Rb, or SO3Ra; wherein each of Ra, Rb, and Rc, independently, is H, C1-C10 alkyl, C3-C20 cycloalkyl, C3-C20 heterocycloalkyl, aryl, or heteroaryl; thereby producing the compound of formula (I) in a one-pot reaction. This invention also relates to the compounds prepared by the method described above.

Abstract: A multiple-gate memory cell comprises a semiconductor body and a plurality of gates arranged in series on the semiconductor body. A charge storage structure on the semiconductor body includes two charge trapping locations beneath each of all or some of the gates in the plurality of gates. Circuitry to conduct source and drain bias voltages to the semiconductor body near a first gate and a last gate in the series, and circuitry to conduct gate bias voltages to the plurality of gates are included. The multiple-gate memory cell includes a continuous, multiple-gate channel region beneath the plurality of gates in the series, with charge storage locations between some or all of the gates.

Abstract: A multiple-gate memory cell comprises a semiconductor body and a plurality of gates arranged in series on the semiconductor body. A charge storage structure on the semiconductor body includes charge trapping locations beneath gates in the plurality of gates. Circuitry to conduct source and drain bias voltages to the semiconductor body near a first gate and a last gate in the series, and circuitry to conduct gate bias voltages to the plurality of gates are included. The multiple-gate memory cell includes a continuous, multiple-gate channel region beneath the plurality of gates in the series, with charge storage locations between some or all of the gates.

Abstract: A method for manufacturing a multiple-gate memory cell which comprises a semiconductor body and a plurality of gates arranged in series and the semiconductor body includes first forming a plurality of gates spaced apart by about a gate width, forming an isolation layer on the sidewalls, and filling between the first plurality of gates to form a second plurality of gates. A charge storage structure is formed on the semiconductor body beneath each of all or some of the gates in the plurality of gates. Circuitry is formed to conduct source and drain bias voltages to the semiconductor body near a first gate and a last gate in the series, and circuitry to conduct gate bias voltages to the plurality of gates is included. The multiple-gate memory cell includes a continuous, multiple-gate channel region beneath the plurality of gates in the series, with charge storage locations between some or all of the gates.

Abstract: An array of multiple-gate memory cells includes sectors. The sectors include at least one row of multiple-gate memory cells. The multiple-gate memory cells comprise a semiconductor body and a plurality of gates arranged in series on the semiconductor body. A charge storage structure on the semiconductor body includes charge trapping locations beneath each of all or some of the gates in the plurality of gates. Word lines and bit lines source and drain bias voltages to the semiconductor body near a first gate and a last gate in the series, and to the plurality of gates are included. The multiple-gate memory cell includes a continuous, multiple-gate channel region beneath the plurality of gates in the series, with charge storage locations between some or all of the gates. Sector select lines are included to couple selected sectors to the bit lines.

Abstract: A multiple-gate memory cell comprises a semiconductor body and a plurality of gates arranged in series on the semiconductor body. A charge storage structure on the semiconductor body includes charge trapping locations beneath gates in the plurality of gates. Circuitry to conduct source and drain bias voltages to the semiconductor body near a first gate and a last gate in the series, and circuitry to conduct gate bias voltages to the plurality of gates are included. The multiple-gate memory cell includes a continuous, multiple-gate channel region beneath the plurality of gates in the series, with charge storage locations between some or all of the gates.

Abstract: A NAND-type erasable programmable read only memory (EEPROM) device formed of a number of substantially identical EEPROM cells with each EEPROM cell being capable of storing two bits of information. A simple method for operating the memory comprises erasing, programming, and reading the device.

Abstract: In a method of manufacturing MOSFET devices, and particularly to the trench-type MOSFET devices, embodiments of the present invention provide methods of forming bottom oxide layers having uniform thickness on the bottom of the trenches and avoiding undesired damage in the partial semiconductor substrate near the top of the trenches. In one embodiment, a method for manufacturing a trench-type MOSFET comprises providing a semiconductor substrate and forming a trench on the semiconductor substrate; forming a first oxide layer on a bottom and sidewalls of the trench and on the semiconductor substrate; forming a bottom anti-reflective coating (BARC) layer in the trench to cover the first oxide layer; forming a photoresist layer on the bottom anti-reflective coating layer; removing the photoresist layer; removing the bottom anti-reflective coating layer; and removing the first oxide layer on the sidewalls of the trench to form a bottom oxide layer on the bottom of the trench.

Abstract: A memory architecture for an integrated circuit comprises a first memory array configured to store data for one pattern of data usage and a second memory array configured to store data for another pattern of data usage. The first and second memory arrays comprise charge storage based nonvolatile memory cells having substantially the same structure in both arrays. A first operation algorithm adapted for example for data flash applications is used for programming, erasing and reading data in the first memory array. A second operation algorithm adapted for example for code flash applications is used for programming, erasing and reading data in the second memory array, wherein the second operation algorithm is different than the first operation algorithm. Thus, one die with memory for both code flash and data flash applications can be easily manufactured using a simple process, at low cost and high yield.

Abstract: An electrically programmable non-volatile memory cell comprises a first electrode, a second electrode and an inter-electrode layer, such as ultra-thin oxide, between the first and second electrodes which is characterized by progressive change in resistance in response to program stress of relatively low voltages. A programmable resistance representing stored data is established by stressing the inter-electrode layer between the electrodes. Embodiments of the memory cell are adapted to store multiple bits of data per cell and/or adapted for programming more than one time without an erase process.

Abstract: Embodiments of the present invention provide a developing method, which can efficiently prevent the developing solution from remaining on the backside surface of the wafer, so as to avoid the influence of the contamination on the subsequent processes. In one embodiment, a developing method comprises providing a wafer in a reaction space, wherein the wafer has an exposed photoresist thereon; coating a developing solution on a surface of the wafer; rotating the wafer; rinsing a normal surface and a backside surface of the wafer; and stopping rinsing the normal surface of the wafer while keeping rinsing the backside surface of the wafer for a specific time period.

Abstract: Provided are a system and method for creating a reticle field layout (RFL). In one example, the method includes receiving information for a RFL design by a computer system directly from a user via a computer interface. The RFL design is automatically verified using predefined specification and design rules accessible to the computer system. The RFL design may be modified by adding additional features before being finalized.

Abstract: A system and method for performing a network planning and mobility management optimization is provided, and it includes a graphical user interface (GUI) front-end for allowing users to operate required procedures for network planning and mobility management optimization. According to this invention, the network plan takes a network topology (NT) and its associated network statistic data as input. Accordingly, a network plan can represent an arrangement of network elements which display a superior-subordinate relationship between network elements in the mobile communication network. Moreover, the network plan comprises a plurality of statistic data reflecting a plurality of user mobility behaviors and a plurality of traffic behaviors of network elements in the mobile communication network.

Abstract: This invention features a compound having the formula: X is O or NR1; and each of Y and Z, independently, is in which each of R1, R2, R3, and R4, independently, is alkyl, cyclyl, heterocyclyl, aralkyl, aryl, or heteroaryl; Ar1 is aralkyl, aryl, or heteroaryl; and Ar2 is cyclyl, heterocyclyl, aralkyl, aryl, or heteroaryl; or Ar1 and Ar2 taken together is heterocyclyl, aralkyl, or heteroaryl. This compound can be used as a red light emitting material in an electro-luminescence device.

Abstract: A method for programming a memory cell is based on applying stress to a memory cell, comprising a first electrode, a second electrode and an inter-electrode layer, to induce a progressive change in a property of the inter-electrode layer. The method includes a verify step including generating a signal, such as a cell current, indicating the value of the property in the selected memory cell. Then, the signal is compared with a reference signal to verify programming of the desired data. Because of the progressive nature of the change, many levels of programming can be achieved. The many levels of programming can be applied for programming a single cell more than once, without an erase process, to programming multiple bits in a single cell, and to a combination of multiple bit and multiple time of programming.

Abstract: An electrically programmable non-volatile memory cell comprises a first electrode, a second electrode and an inter-electrode layer, such as ultra-thin oxide, between the first and second electrodes which is characterized by progressive change in resistance in response to program stress of relatively low voltages. A programmable resistance representing stored data is established by stressing the inter-electrode layer between the electrodes. Embodiments of the memory cell are adapted to store multiple bits of data per cell and/or adapted for programming more than one time without an erase process.

Abstract: A method for manufacturing an electrically programmable non-volatile memory cell comprises forming a first electrode on a substrate, forming an inter-electrode layer of material on the first electrode having a property which is characterized by progressive change in response to stress, and forming a second electrode over the inter-electrode layer of material. The inter-electrode layer comprises a dielectric layer, such as ultra-thin oxide, between the first and second electrodes. A programmable resistance, or other property, is established by stressing the dielectric layer, representing stored data. Embodiments of the memory cell are adapted to store multiple bits of data per cell and/or adapted for programming more than one time without an erase process.

Abstract: A discharge lamp circuit for ignition time control and overvoltage protection. The discharge lamp circuit includes drive circuitry, a sensing circuit, a timing circuit and a start-up circuit. The drive circuitry produces a strike voltage for a discharge lamp and provides a lamp current through the discharge lamp. The sensing circuit is provided to detect the lamp current. During lamp start-up, the timing circuit will develop a threshold voltage at the end of a predetermined period if the discharge lamp has not been lit yet, thereby controlling an ignition time of the drive circuitry. The start-up circuit allows the drive circuitry to keep on applying the strike voltage for the ignition time in order to start the discharge lamp before the threshold voltage is developed. Once the sensing circuit detects the absence of the lamp current, the start-up circuit also causes the drive circuitry shutdown.