Patents by Inventor Chih-Yu Chang

Chih-Yu Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12040036
    Abstract: The present disclosure describes a magnetic memory device. The magnetic memory device includes a magnetic sensing array configured to sense an external magnetic field strength. The magnetic memory device further includes a voltage modulator configured to, in response to the external magnetic field strength being greater than a threshold magnetic field strength, provide a test voltage different from a current write voltage of the magnetic memory device. The magnetic memory device further includes an error check array configured to use the test voltage as a write voltage of the error check array and provide a bit error rate corresponding to the test voltage. The magnetic memory device further includes a control unit configured to adjust, based on the bit error rate being equal to or less than a threshold bit error rate, a write voltage of the magnetic memory device from the current write voltage to the test voltage.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: July 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Hsiang Chen, Chih-Yang Chang, Chia Yu Wang, Meng-Chun Shih
  • Patent number: 12040273
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a fin disposed over a substrate, a gate structure disposed over a channel region of the fin, such that the gate structure traverses source/drain regions of the fin, a device-level interlayer dielectric (ILD) layer of a multi-layer interconnect structure disposed over the substrate, wherein the device-level ILD layer includes a first dielectric layer, a second dielectric layer disposed over the first dielectric layer, and a third dielectric layer disposed over the second dielectric layer, wherein a material of the third dielectric layer is different than a material of the second dielectric layer and a material of the first dielectric layer. The semiconductor device further comprises a gate contact to the gate structure disposed in the device-level ILD layer and a source/drain contact to the source/drain regions disposed in the device-level ILD layer.
    Type: Grant
    Filed: October 18, 2022
    Date of Patent: July 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Lin-Yu Huang, Sheng-Tsung Wang, Jia-Chuan You, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 12040387
    Abstract: Circuit devices and methods of forming the same are provided. In one embodiment, a method includes receiving a workpiece that includes a substrate and a fin extending from the substrate, forming a first ferroelectric layer on the fin, forming a dummy gate structure over a channel region of the fin, forming a gate spacer over sidewalls of the dummy gate structure, forming an inter-level dielectric layer over the workpiece, removing the dummy gate structure to expose the first ferroelectric layer over the channel region of the fin, and forming a gate electrode over the exposed first ferroelectric layer over the channel region of the fin.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: July 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Bo-Feng Young, Chih-Yu Chang, Sai-Hooi Yeong, Chi On Chui, Chih-Hao Wang
  • Publication number: 20240213367
    Abstract: The present disclosure relates a ferroelectric field-effect transistor (FeFET) device. In some embodiments, the FeFET device includes a ferroelectric layer having a first side and a second side opposite to the first side and a gate electrode disposed along the first side of the ferroelectric layer. The FeFET device further includes an OS channel layer disposed along the second side of the ferroelectric layer opposite to the first side and a pair of source/drain regions disposed on opposite sides of the OS channel layer. The FeFET device further includes a 2D contacting layer disposed along the OS channel layer. The OS channel layer has a first doping type, and the 2D contacting layer has a second doping type different than the first doping type.
    Type: Application
    Filed: March 7, 2024
    Publication date: June 27, 2024
    Inventors: Mauricio Manfrini, Chih-Yu Chang, Sai-Hooi Yeong
  • Publication number: 20240206185
    Abstract: The present disclosure relates to an integrated chip device. The integrated chip device includes a plurality of conductive lines disposed over a substrate. The plurality of conductive lines are stacked onto one another and are separated from one another by dielectric layers interleaved between adjacent ones of the plurality of conductive lines. A ferroelectric layer is along sidewalls of the plurality of conductive lines and the dielectric layers. The ferroelectric layer separates a channel layer from the plurality of conductive lines. A species is disposed within the ferroelectric layer. The species has a concentration that decreases from the channel layer towards a surface of the ferroelectric layer that faces away from the channel layer.
    Type: Application
    Filed: February 29, 2024
    Publication date: June 20, 2024
    Inventors: Chun-Chieh Lu, Sai-Hooi Yeong, Bo-Feng Young, Yu-Ming Lin, Chih-Yu Chang
  • Publication number: 20240186414
    Abstract: The present disclosure relates to a semiconductor device includes a substrate and first and second spacers on the substrate. The semiconductor device includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers. The first portion includes a crystalline material and the second portion comprises an amorphous material. The gate stack further includes a gate electrode on the first and second portions of the gate dielectric layer.
    Type: Application
    Filed: January 2, 2024
    Publication date: June 6, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Ming LIN, Sai-Hooi YEONG, Ziwei FANG, Bo-Feng YOUNG, Chi On CHUI, Chih-Yu CHANG, Huang-Lin CHAO
  • Patent number: 11997854
    Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes: receiving a substrate; forming a transistor surrounded by a dielectric layer over the substrate, wherein the dielectric layer includes a through hole, and the transistor is formed in the through hole; forming a gate contact in the through hole to electrically connect the transistor; forming a ferroelectric layer over the gate contact in the through hole; forming an insulating layer conformal to and over the dielectric layer and the ferroelectric layer; removing a portion of the insulating layer to form a spacer in the through hole and over the ferroelectric layer; and forming a top electrode over the ferroelectric layer and between the spacer.
    Type: Grant
    Filed: May 20, 2022
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chih-Yu Chang, Sai-Hooi Yeong, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20240172433
    Abstract: A method for fabricating a three-dimensional memories is provided. A stack with multiple levels is formed, and each of the levels includes an isolation layer, a metal layer, and a semiconductor layer between the isolation layer and the metal layer. A first trench and a plurality of second trenches are formed along each parallel line in the stack of the levels. The isolation layers and the metal layers in the parallel lines are removed through the first trench and the second trenches, so as to expose the semiconductor layers in the parallel line. A plurality of memory cells are formed in the parallel lines of the levels. In each of the levels, each of the memory cells includes a transistor and a channel of the transistor is formed by the semiconductor layer in the parallel line.
    Type: Application
    Filed: February 1, 2024
    Publication date: May 23, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Feng YOUNG, Sai-Hooi YEONG, Chih-Yu CHANG, Han-Jong CHIA, Chenchen Jacob WANG, Yu-Ming LIN
  • Patent number: 11989077
    Abstract: A management circuit is coupled to multiple processor cores for performing current suppression. The management circuit includes a detection circuit and a throttle signal generator. The detection circuit is operative to receive an activity signal from each processor core, and estimate a total current consumed by the plurality of processor cores based on activity signals. The activity signal indicates a current index proportional to current consumption of the processor core in a given time period. The throttle signal generator is operative to assert or de-assert throttle signals to the processor cores, one processor core at a time, based on one or more metrics calculated from the total current.
    Type: Grant
    Filed: July 16, 2022
    Date of Patent: May 21, 2024
    Assignee: MediaTek Inc.
    Inventors: Hung-Wei Wu, Chih-Yu Chang
  • Patent number: 11991888
    Abstract: Memory devices and methods of forming the memory devices are disclosed herein. The memory devices include a resistive memory array including a first resistive memory cell, a staircase contact structure adjacent the resistive memory array, and an inter-metal dielectric layer over the staircase contact structure. The memory devices further include a first diode and a second diode over the inter-metal dielectric layer. The memory devices further include a first conductive via electrically coupling the first diode to a first resistor of the first resistive memory cell and a second conductive via electrically coupling the second diode to a second resistor of the first resistive memory cell.
    Type: Grant
    Filed: June 29, 2023
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Han Lin, Chih-Yu Chang, Han-Jong Chia, Sai-Hooi Yeong, Yu-Ming Lin
  • Patent number: 11974441
    Abstract: A 3D memory array in which epitaxial source/drain regions which are horizontally merged and vertically unmerged are used as source lines and bit lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a first channel region over a semiconductor substrate; a first epitaxial region electrically coupled to the first channel region; a second epitaxial region directly over the first epitaxial region in a direction perpendicular to a major surface of the semiconductor substrate; a dielectric material between the first epitaxial region and the second epitaxial region, the second epitaxial region being isolated from the first epitaxial region by the dielectric material; a gate dielectric surrounding the first channel region; and a gate electrode surrounding the gate dielectric.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bo-Feng Young, Sai-Hooi Yeong, Chih-Yu Chang, Chi On Chui, Yu-Ming Lin
  • Patent number: 11955548
    Abstract: The present disclosure relates a ferroelectric field-effect transistor (FeFET) device. In some embodiments, the FeFET device includes a ferroelectric layer having a first side and a second side opposite to the first side and a gate electrode disposed along the first side of the ferroelectric layer. The FeFET device further includes an OS channel layer disposed along the second side of the ferroelectric layer opposite to the first side and a pair of source/drain regions disposed on opposite sides of the OS channel layer. The FeFET device further includes a 2D contacting layer disposed along the OS channel layer. The OS channel layer has a first doping type, and the 2D contacting layer has a second doping type different than the first doping type.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mauricio Manfrini, Chih-Yu Chang, Sai-Hooi Yeong
  • Patent number: 11950427
    Abstract: A memory cell includes a transistor over a semiconductor substrate. The transistor includes a ferroelectric layer arranged along a sidewall of a word line. The ferroelectric layer includes a species with valence of 5, valence of 7, or a combination thereof. An oxide semiconductor layer is electrically coupled to a source line and a bit line. The ferroelectric layer is disposed between the oxide semiconductor layer and the word line.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Lu, Sai-Hooi Yeong, Bo-Feng Young, Yu-Ming Lin, Chih-Yu Chang
  • Publication number: 20240107776
    Abstract: An antiferroelectric field effect transistor (Anti-FeFET) of a memory cell includes an antiferroelectric layer instead of a ferroelectric layer. The antiferroelectric layer may operate based on a programmed state and an erased state in which the antiferroelectric layer is in a fully polarized alignment and a non-polarized alignment (or a random state of polarization), respectively. This enables the antiferroelectric layer in the FeFET to provide a sharper/larger voltage drop for an erase operation of the FeFET (e.g., in which the FeFET switches or transitions from the programmed state to the erased state) relative to a ferroelectric material layer that operates based on switching between two opposing fully polarized states.
    Type: Application
    Filed: January 5, 2023
    Publication date: March 28, 2024
    Inventors: Chun-Chieh LU, Chih-Yu CHANG, Yu-Chuan SHIH, Huai-Ying HUANG, Yu-Ming LIN
  • Publication number: 20240096928
    Abstract: A semiconductor structure and manufacturing method thereof are provided. The semiconductor structure includes a substrate and a metallization structure over the substrate. The metallization structure includes a MIM structure, a first contact and a second contact. The MIM structure includes a bottom electrode layer, a dielectric layer on the bottom electrode layer, a ferroelectric layer on the dielectric layer, and a top electrode layer on the ferroelectric layer. The ferroelectric layer is substantially made of lead zirconate titanate (PZT), BaTiO3 (BTO), or barium strontium titanate (BST), and a thickness of the ferroelectric layer is greater than a thickness of the dielectric layer.
    Type: Application
    Filed: November 24, 2023
    Publication date: March 21, 2024
    Inventors: SAI-HOOI YEONG, CHIH-YU CHANG, CHUN-YEN PENG, CHI ON CHUI
  • Publication number: 20240096388
    Abstract: A memory cell includes a read word line extending in a first direction, a write transistor, and a read transistor coupled to the write transistor. The read transistor includes a ferroelectric layer, a drain terminal of the read transistor directly connected to the read word line, and a source terminal of the read transistor coupled to a first node. The write transistor is configured to adjust a polarization state of the read transistor, the polarization state corresponding to a stored data value of the memory cell.
    Type: Application
    Filed: November 24, 2023
    Publication date: March 21, 2024
    Inventors: Bo-Feng YOUNG, Sai-Hooi YEONG, Chao-I WU, Chih-Yu CHANG, Yu-Ming LIN
  • Publication number: 20240085369
    Abstract: Disclosed is a self-powered formaldehyde sensing device, comprising: a triboelectric material electrode layer including a first substrate and a first electrode layer formed on the first substrate; a triboelectric material dielectric layer including a second substrate, a second electrode layer formed on the second substrate, a dielectric reacting layer formed on the second electrode layer, and a reaction modification layer formed on the dielectric reacting layer to surface-modify the dielectric reacting layer, the reaction modification layer being a phosphomolybdic acid complex (cPMA) layer, the phosphomolybdic acid complex of the phosphomolybdic acid complex layer being obtained by dissolving 4,4?-bipyridine (BPY) in isopropanol (IPA) and then mixing with phosphomolybdic acid (PMA) solution; an elastic spacer; and an external circuit.
    Type: Application
    Filed: December 21, 2022
    Publication date: March 14, 2024
    Applicant: National Taiwan University of Science and Technology
    Inventors: Chih-Yu Chang, Chun-Yi Ho, Yu-Hsuan Cheng, Ying-Ying Chen
  • Publication number: 20240079472
    Abstract: The present disclosure provides a semiconductor device and a method for forming a semiconductor device. The semiconductor device includes a substrate, and a first gate dielectric stack over the substrate, wherein the first gate dielectric stack includes a first ferroelectric layer, and a first dielectric layer coupled to the first ferroelectric layer, wherein the first ferroelectric layer includes a first portion made of a ferroelectric material in orthorhombic phase, a second portion made of the ferroelectric material in monoclinic phase, and a third portion made of the ferroelectric material in tetragonal phase, wherein a total volume of the second portion is greater than a total volume of the first portion, and the total volume of the first portion is greater than a total volume of the third portion.
    Type: Application
    Filed: November 6, 2023
    Publication date: March 7, 2024
    Inventors: CHUN-YEN PENG, TE-YANG LAI, BO-FENG YOUNG, CHIH-YU CHANG, SAI-HOOI YEONG, CHI ON CHUI
  • Patent number: 11901450
    Abstract: The present disclosure relates to a semiconductor device includes a substrate and first and second spacers on the substrate. The semiconductor device includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers. The first portion includes a crystalline material and the second portion comprises an amorphous material. The gate stack further includes a gate electrode on the first and second portions of the gate dielectric layer.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semicondutor Manufacturing Co., Ltd.
    Inventors: Cheng-Ming Lin, Sai-Hooi Yeong, Ziwei Fang, Bo-Feng Young, Chi On Chui, Chih-Yu Chang, Huang-Lin Chao
  • Patent number: 11903189
    Abstract: Three-dimensional memories are provided. A three-dimensional memory includes a plurality of memory cells, a plurality of word lines, a plurality of bit lines and a plurality of source lines. The memory cells are divided into a plurality of groups, and the groups of memory cells are formed in respective levels stacked along a first direction. The word lines extend along a second direction, and the second direction is perpendicular to the first direction. Each of the bit lines includes a plurality of sub-bit lines formed in the respective levels. Each of the source lines includes a plurality of sub-source lines formed in respective levels. In each of the levels, the memory cells of the corresponding group are arranged in a plurality of columns, and the sub-bit lines and the sub-source lines are alternately arranged between two adjacent columns.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bo-Feng Young, Sai-Hooi Yeong, Chih-Yu Chang, Han-Jong Chia, Chenchen Jacob Wang, Yu-Ming Lin