Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate. A first precursor and a second precursor are combined. The first precursor is an organometallic having a formula: MaRbXc, where M is one or more of Sn, Bi, Sb, In, and Te, R is one or more of a C7-C11 aralkyl group, a C3-C10 cycloalkyl group, a C2-C10 alkoxy group, and a C2-C10 alkylamino group, X is one or more of a halogen, a sulfonate group, and an alkylamino group, and 1?a?2, b?1, c?1, and b+c?4, and the second precursor is one or more of water, an amine, a borane, and a phosphine. The photoresist layer is selectively exposed to actinic radiation to form a latent pattern. The latent pattern is developed by applying a developer to the selectively exposed photoresist layer.

Abstract: A memory cell includes a transistor including a memory film extending along a word line; a channel layer extending along the memory film, wherein the memory film is between the channel layer and the word line; a source line extending along the memory film, wherein the memory film is between the source line and the word line; a first contact layer on the source line, wherein the first contact layer contacts the channel layer and the memory film; a bit line extending along the memory film, wherein the memory film is between the bit line and the word line; a second contact layer on the bit line, wherein the second contact layer contacts the channel layer and the memory film; and an isolation region between the source line and the bit line.

Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip including forming a ferroelectric layer over a bottom electrode layer, forming a top electrode layer over the ferroelectric layer, performing a first removal process to remove peripheral portions of the bottom electrode layer, the ferroelectric layer, and the top electrode layer, and performing a second removal process using a second etch that is selective to the bottom electrode layer and the top electrode layer to remove portions of the bottom electrode layer and the top electrode layer, so that after the second removal process the ferroelectric layer has a surface that protrudes past a surface of the bottom electrode layer and the top electrode layer.

Abstract: The present disclosure relates a device. The device includes a ferroelectric structure having a first side and a second side. A gate structure is disposed along the first side of the ferroelectric structure. An oxide semiconductor is disposed along the second side of the ferroelectric structure and has a first semiconductor conductivity type. A source and a drain are disposed on the oxide semiconductor. A semiconductor layer is arranged on the oxide semiconductor between sidewalls of the source and the drain. The semiconductor layer includes a semiconductor material having a second semiconductor conductivity type that is different than the first semiconductor conductivity type. The semiconductor layer includes p-doped silicon, p-doped germanium, n-doped silicon, or n-doped germanium.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a source/drain epitaxial feature disposed over a substrate, and the source/drain epitaxial feature includes about 0.002 atomic percent to about 0.02 atomic percent of aluminum. The structure further includes a first semiconductor layer in contact with the source/drain epitaxial feature and a gate electrode layer disposed over the first semiconductor layer.

Abstract: A system for notifying environmental pollution status includes wireless environment sensing devices and a portable wireless environmental pollution status notification device. The wireless environment sensing devices, respectively arranged in the different sensing locations of a physical environment, respectively store the sensing locations and respectively sense pollution related information corresponding to the different sensing locations to output the pollution related information and the sensing locations corresponding thereto. The portable wireless environmental pollution status notification device, wirelessly connected to the plurality of wireless environment sensing devices and located in the physical environment, receives the pollution related information and the sensing locations corresponding thereto and generates notification signals based on the pollution related information and the sensing locations corresponding thereto.

Abstract: A method for rendering data of a three-dimensional image adapted to an eye position and a display system are provided. The method is used to render the three-dimensional image to be displayed in a three-dimensional space. In the method, a three-dimensional image data used to describe the three-dimensional image is obtained. The eye position of a user is detected. The ray-tracing information between the eye position and each lens unit of a multi-optical element module forms a region of visibility (RoV) that may cover a portion of the three-dimensional image in the three-dimensional space. When coordinating the physical characteristics of a display panel and the multi-optical element module, a plurality of elemental images can be obtained. The elemental images form an integral image that records the three-dimensional image data adapted to the eye position, and the integral image is used to reconstruct the three-dimensional image.

Abstract: A semiconductor fabrication method includes: forming an epitaxial stack including at least one sacrificial epitaxial layer and at least one channel epitaxial layer; forming a plurality of fins in the epitaxial stack; performing tuning operations to prevent a width of the sacrificial epitaxial layer expanding beyond a width of the channel epitaxial layer during operations to form isolation features; forming the isolation features between the plurality of fins, wherein the width of the sacrificial epitaxial layer does not expand beyond the width of the channel epitaxial layer; forming a sacrificial gate stack; forming gate sidewall spacers on sidewalls of the sacrificial gate stack; forming inner spacers around the sacrificial epitaxial layer and the channel epitaxial layer; forming source/drain features; removing the sacrificial gate stack and sacrificial epitaxial layer; and forming a replacement metal gate, wherein the metal gate is shielded from the source/drain features.

Abstract: A positioning pollutant-measuring system includes a cloud server, a wireless base station, an automatic moving vehicle, and a positioning pollutant-measuring device. The automatic moving vehicle carries the positioning pollutant-measuring device and passes through different locations. The positioning pollutant-measuring device receives location related parameters from the wireless base station and measures the air flow rates or the air humidity of the different locations to adjust a resolution for measuring pollutants corresponding to the different locations.

Abstract: In some embodiments, a semiconductor wafer testing system is provided. The semiconductor wafer testing system includes a semiconductor wafer prober having one or more conductive probes, where the semiconductor wafer prober is configured to position the one or more conductive probes on an integrated chip (IC) that is disposed on a semiconductor wafer. The semiconductor wafer testing system also includes a ferromagnetic wafer chuck, where the ferromagnetic wafer chuck is configured to hold the semiconductor wafer while the wafer prober positions the one or more conductive probes on the IC. An upper magnet is disposed over the ferromagnetic wafer chuck, where the upper magnet is configured to generate an external magnetic field between the upper magnet and the ferromagnetic wafer chuck, and where the ferromagnetic wafer chuck amplifies the external magnetic field such that the external magnetic field passes through the IC with an amplified magnetic field strength.

Abstract: The present disclosure relates to an integrated chip including a substrate and a pixel. The pixel includes a photodetector. The photodetector is in the substrate. The integrated chip further includes a first inner trench isolation structure and an outer trench isolation structure that extend into the substrate. The first inner trench isolation structure laterally surrounds the photodetector in a first closed loop. The outer trench isolation structure laterally surrounds the first inner trench isolation structure along a boundary of the pixel in a second closed loop and is laterally separated from the first inner trench isolation structure. Further, the integrated chip includes a scattering structure that is defined, at least in part, by the first inner trench isolation structure and that is configured to increase an angle at which radiation impinges on the outer trench isolation structure.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes an active region including a channel region and a source/drain region and extending along a first direction, and a source/drain contact structure over the source/drain region. The source/drain contact structure includes a base portion extending lengthwise along a second direction perpendicular to the first direction, and a via portion over the base portion. The via portion tapers away from the base portion.

Abstract: A method of forming a nanosheet FET is provided. A plurality of first and second semiconductor layers are alternately formed on a substrate. The first and second semiconductor layers are patterned into a plurality of stacks of semiconductor layers separate from each other by a space along a direction. Each stack of semiconductor layers has a cross-sectional view along the direction gradually widening towards the substrate. An epitaxial feature is formed in each of the spaces. The patterned second semiconductor layers are then removed from each of the stacks of semiconductor layers.

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. A method according one embodiment of the present disclosure include forming a stack over a substrate, forming a fin-shape structure from patterning the stack and the substrate, recessing the fin-shape structure to form a source/drain trench, depositing a dielectric film in the source/drain trench with a top surface below a top surface of the substrate in the fin-shape structure, and forming an epitaxial feature over the dielectric film. A bottom surface of the epitaxial feature is below the top surface of the substrate in the fin-shape structure.

Abstract: Various embodiments of the present disclosure provide a semiconductor device structure. In one embodiment, the semiconductor device structure includes a first source/drain feature and a second source/drain feature, a plurality of semiconductor layers vertically stacked and disposed between the first and second source/drain features, a gate electrode layer surrounding a portion of each of the plurality of the semiconductor layers, and an interfacial layer (IL) disposed between the gate electrode layer and one of the plurality of the semiconductor layers, wherein a topmost semiconductor layer of the plurality of the semiconductor layers has a first length, and the IL has a second length greater than the first length.

Abstract: The present disclosure, in some embodiments, relates to a ferroelectric memory device. The ferroelectric memory device includes a multi-layer stack disposed on a substrate. The multi-layer stack has a plurality of conductive layers and a plurality of dielectric layers stacked alternately. A channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. A ferroelectric layer is disposed between the channel layer and both of the plurality of conductive layers and the plurality of dielectric layers. A plurality of oxygen scavenging layers are disposed along sidewalls of the plurality of conductive layer. The plurality of oxygen scavenging layers laterally separate the ferroelectric layer from the plurality of conductive layers.

Abstract: The present disclosure relates a ferroelectric field-effect transistor (FeFET) device. The FeFET device includes a ferroelectric structure having a first side and a second side. A gate structure is disposed along the first side of the ferroelectric structure, and an oxide semiconductor is disposed along the second side of the ferroelectric structure. The oxide semiconductor has a first semiconductor type. A source region and a drain region are disposed on the oxide semiconductor. The gate structure is laterally between the source region and the drain region. A polarization enhancement structure is arranged on the oxide semiconductor between the source region and the drain region. The polarization enhancement structure includes a semiconductor material or an oxide semiconductor material having a second semiconductor type that is different than the first semiconductor type.

Abstract: Embodiments include structures and methods for fabricating an MFM capacitor having a plurality of metal contacts. An embodiment may include a first metal strip, disposed on a substrate and extending in a first direction, a ferroelectric blanket layer, disposed on the first metal strip, a second metal strip, disposed on the ferroelectric blanket layer and extending in a second direction different from the first direction, and a plurality of metal contacts disposed between the first metal strip and the second metal strip and located within an intersection region of the first metal strip and the second metal strip.

Abstract: A semiconductor chip including a semiconductor substrate, an interconnect structure and a memory cell array is provided. The semiconductor substrate includes a logic circuit. The interconnect structure is disposed on the semiconductor substrate and electrically connected to the logic circuit, and the interconnect structure includes stacked interlayer dielectric layers and interconnect wirings embedded in the stacked interlayer dielectric layers. The memory cell array is embedded in the stacked interlayer dielectric layers. The memory cell array includes driving transistors and memory devices, and the memory devices are electrically connected the driving transistors through the interconnect wirings.