Abstract: The present disclosure provides a semiconductor structure and a method for forming a semiconductor structure. The method for forming a semiconductor structure includes forming a semiconductor stack over a substrate, wherein the semiconductor stack includes a plurality of first semiconductor layers and a plurality of second semiconductor layers alternatively stacked, patterning the semiconductor stack to form a first fin and a second fin adjacent to the first fin, and removing the second semiconductor layers to obtain a first group of nanosheets over the first fin and a second group of nanosheets over the second fin, wherein a lateral spacing between one of the nanosheets in the first group and a corresponding nanosheet in the second group is smaller than a vertical spacing between each of the nanosheets in the first group.

Abstract: Embodiments include structures and methods for fabricating an MFM capacitor having a plurality of metal contacts. An embodiment may include a first metal strip, disposed on a substrate and extending in a first direction, a ferroelectric blanket layer, disposed on the first metal strip, a second metal strip, disposed on the ferroelectric blanket layer and extending in a second direction different from the first direction, and a plurality of metal contacts disposed between the first metal strip and the second metal strip and located within an intersection region of the first metal strip and the second metal strip.

Abstract: A semiconductor chip including a semiconductor substrate, an interconnect structure and a memory cell array is provided. The semiconductor substrate includes a logic circuit. The interconnect structure is disposed on the semiconductor substrate and electrically connected to the logic circuit, and the interconnect structure includes stacked interlayer dielectric layers and interconnect wirings embedded in the stacked interlayer dielectric layers. The memory cell array is embedded in the stacked interlayer dielectric layers. The memory cell array includes driving transistors and memory devices, and the memory devices are electrically connected the driving transistors through the interconnect wirings.

Abstract: A memory cell includes a transistor over a semiconductor substrate. The transistor includes a ferroelectric layer arranged along a sidewall of a word line. The ferroelectric layer includes a species with valence of 5, valence of 7, or a combination thereof. An oxide semiconductor layer is electrically coupled to a source line and a bit line. The ferroelectric layer is disposed between the oxide semiconductor layer and the word line.

Abstract: A ferroelectric memory device includes a multi-layer stack, a channel layer, a ferroelectric layer and oxygen scavenging layers. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. The ferroelectric layer is disposed between the channel layer and both of the plurality of conductive layers and the plurality of dielectric layers. The oxygen scavenging layers are disposed along sidewalls of the plurality of conductive layer. The plurality of oxygen scavenging layers laterally separate the ferroelectric layer from the plurality of conductive layers.

Abstract: Negative capacitance field-effect transistor (NCFET) and ferroelectric field-effect transistor (FE-FET) devices and methods of forming are provided. The gate dielectric stack includes a ferroelectric gate dielectric layer. An amorphous high-k dielectric layer and a dopant-source layer are deposited sequentially followed by a post-deposition anneal (PDA). The PDA converts the amorphous high-k layer to a polycrystalline high-k film with crystalline grains stabilized by the dopants in a crystal phase in which the high-k dielectric is a ferroelectric high-k dielectric. After the PDA, the remnant dopant-source layer may be removed. A gate electrode is formed over remnant dopant-source layer (if present) and the polycrystalline high-k film.

Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes an oxide semiconductor nanostructure suspended over a substrate. The semiconductor device structure also includes a source/drain structure adjacent to the oxide semiconductor nanostructure. The source/drain structure contains oxygen, and the oxide semiconductor nanostructure has a greater atomic concentration of oxygen than that of the source/drain structure. The semiconductor device structure further includes a gate stack wrapping around the oxide semiconductor nanostructure.

Abstract: The present disclosure relates to a semiconductor device includes a substrate and first and second spacers on the substrate. The semiconductor device includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers. The first portion includes a crystalline material and the second portion comprises an amorphous material. The gate stack further includes a gate electrode on the first and second portions of the gate dielectric layer.

Abstract: The present disclosure provides a semiconductor device, including a substrate, a fin over the substrate, a multilayer gate dielectric stack over the fin, wherein the multilayer gate dielectric stack includes a first ferroelectric layer, and a first dielectric layer coupled to the first ferroelectric layer, and a gate over the multilayer gate dielectric stack.

Abstract: A method includes following steps. A silicon germanium layer is formed on a substrate. A surface layer of the silicon germanium layer is oxidized to form an interfacial layer comprising silicon oxide and germanium oxide. The interfacial layer is nitridated. A metal gate structure is formed over the nitridated interfacial layer.

Abstract: Negative capacitance field-effect transistor (NCFET) and ferroelectric field-effect transistor (FE-FET) devices and methods of forming are provided. The gate dielectric stack includes a ferroelectric gate dielectric layer. An amorphous high-k dielectric layer and a dopant-source layer are deposited sequentially followed by a post-deposition anneal (PDA). The PDA converts the amorphous high-k layer to a polycrystalline high-k film with crystalline grains stabilized by the dopants in a crystal phase in which the high-k dielectric is a ferroelectric high-k dielectric. After the PDA, the remnant dopant-source layer may be removed. A gate electrode is formed over remnant dopant-source layer (if present) and the polycrystalline high-k film.

Abstract: The present disclosure provides a semiconductor structure, including a substrate having a memory region and a logic region, the memory region including a first group of nanosheets vertically arranged over a first region of the substrate, wherein the first group of nanosheets includes: a first semiconductor nanosheet, a second group of nanosheets vertically arranged over a second region of the substrate adjacent to the first region, wherein the second group of nanosheets includes: a second semiconductor nanosheet, and a third semiconductor nanosheet over the second semiconductor nanosheet, a first metal gate layer surrounding the first semiconductor nanosheet, and a second metal gate layer surrounding the second semiconductor nanosheet, wherein the first metal gate layer is in direct contact with the second metal gate layer.

Abstract: Various embodiments of the present disclosure are directed towards a ferroelectric memory device. The ferroelectric memory device includes a pair of source/drain regions disposed in a substrate. A gate dielectric is disposed over the substrate and between the source/drain regions. A gate electrode is disposed on the gate dielectric. A polarization switching structure is disposed on the gate electrode. A pair of sidewall spacers is disposed over the substrate and along opposite sidewalls of the gate electrode and the polarization switching structure.

Abstract: The present disclosure provides a semiconductor device, including a substrate, a metal gate layer over the substrate, a channel between a source region and a drain region in the substrate, and a ferroelectric layer between the metal gate layer and the substrate, wherein the ferroelectric layer is configured to cause a strain in the channel when applied with an electrical field.

Abstract: The present disclosure relates to a semiconductor device includes a substrate and first and second spacers on the substrate. The semiconductor device includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers. The first portion includes a crystalline material and the second portion comprises an amorphous material. The gate stack further includes a gate electrode on the first and second portions of the gate dielectric layer.

Abstract: The present disclosure provides a semiconductor structure, including a substrate having a memory region and a logic region, the memory region including a first group of nanosheets vertically arranged over a first region of the substrate, wherein the first group of nanosheets includes: a first semiconductor nanosheet, a second group of nanosheets vertically arranged over a second region of the substrate adjacent to the first region, wherein the second group of nanosheets includes: a second semiconductor nanosheet, and a third semiconductor nanosheet over the second semiconductor nanosheet, a first metal gate layer surrounding the first semiconductor nanosheet, and a second metal gate layer surrounding the second semiconductor nanosheet, wherein the first metal gate layer is in direct contact with the second metal gate layer.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a source/drain structure, a metal gate structure, a ferroelectric layer, a spacer and a metal layer. The source/drain structure is disposed over the substrate. The metal gate structure is disposed over the substrate and between the source/drain structure. The ferroelectric layer is disposed over the metal gate structure and the source/drain structure. The spacer is disposed over the ferroelectric layer. The metal layer is disposed over the ferroelectric layer and surrounded by the spacer. A method for manufacturing a semiconductor structure is also provided.

Abstract: A MIM structure and manufacturing method thereof are provided. The MIM structure includes a substrate having a first surface and a metallization structure over the substrate. The metallization structure includes a bottom electrode layer, a dielectric layer on the bottom electrode layer, a ferroelectric layer on the dielectric layer, a top electrode layer on the ferroelectric layer, a first contact electrically coupled to the top electrode layer, and a second contact penetrating the dielectric layer and the ferroelectric layer, electrically coupled to the bottom electrode layer.

Abstract: A semiconductor device includes a source region, a drain region, a SiGe channel region, an interfacial layer, a high-k dielectric layer and a gate electrode. The source region and the drain region are over a substrate. The SiGe channel region is laterally between the source region and the drain region. The interfacial layer forms a nitrogen-containing interface with the SiGe channel region. The high-k dielectric layer is over the interfacial layer. The gate electrode is over the high-k dielectric layer.

Abstract: A composite textile product includes a polyamide textile layer and a polyamide film. The polyamide film is bonded to the polyamide textile layer. A thickness of the polyamide textile layer is between 0.1 mm and 0.3 mm. The polyamide film has an average pore size ranging from 10 ?m to 150 ?m. A thickness of the polyamide film is between 0.01 mm and 0.1 mm. Wherein the polyamide film comprises a copolymer material, and the copolymer material includes a polyamide section and a polyether section.