Patents by Inventor Chiharu Ota
Chiharu Ota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220020853Abstract: A semiconductor device of embodiments includes a silicon carbide layer having a first face and a second face, a gate electrode, a gate insulating layer on the first face. The silicon carbide layer includes a first silicon carbide region of a first conductive type; a second silicon carbide region of a second conductive type disposed between the first silicon carbide region and the first face; a third silicon carbide region of a second conductive type between the first silicon carbide region and the first face; a fourth silicon carbide region; a fifth silicon carbide region; a sixth silicon carbide region of a second conductive type between the first silicon carbide region and the first face and between the second silicon carbide region and the third silicon carbide region; and a crystal defect. The crystal defect is in the sixth silicon carbide region.Type: ApplicationFiled: July 16, 2021Publication date: January 20, 2022Inventors: Takuma Suzuki, Sozo Kanie, Chiharu Ota, Susumu Obata, Kazuhisa Goto
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Publication number: 20220005925Abstract: This semiconductor device according to an embodiment includes: a silicon carbide layer; a gate electrode; a silicon oxide layer between the silicon carbide layer and the gate electrode; and a region between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration not less than 1×1021cm?3. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region has its peak in the region, and a state density Z1/2 in a portion is not more than 1×1011cm?3. The portion is within 100 nm from the silicon oxide layer toward the silicon carbide layer. A nitrogen concentration and a carbon concentration in a position 1 nm from the peak toward the silicon oxide layer is not more than 1×1018cm?3, and a nitrogen concentration in a position 1 nm from the peak toward the silicon carbide layer is not more than 1×1018cm?3.Type: ApplicationFiled: February 16, 2021Publication date: January 6, 2022Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tatsuo SHIMIZU, Yukio NAKABAYASHI, Johji NISHIO, Chiharu OTA, Toshihide ITO
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Publication number: 20210367040Abstract: According to one embodiment, a semiconductor device includes a silicon carbide member, first, second, and third electrodes, and a first insulating member. The silicon carbide member includes first, second, and third silicon carbide regions. The first silicon carbide region includes first, second, third, and fourth partial regions. The third partial region is between the first and second partial regions. The fourth partial region is between the third partial region and the first electrode. The second silicon carbide region includes first and second semiconductor regions. The third silicon carbide region includes third and fourth semiconductor regions. The first insulating member includes first, second, and third insulating regions. The second electrode is electrically connected to the first silicon carbide region. The third and fourth partial regions are between the second and first electrodes. The third electrode is electrically connected to the second silicon carbide region.Type: ApplicationFiled: January 26, 2021Publication date: November 25, 2021Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yukio NAKABAYASHI, Tatsuo SHIMIZU, Toshihide ITO, Chiharu OTA, Johji NISHIO
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Patent number: 11152470Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include a first process of causing a stacking fault of a first semiconductor layer to expand. The first semiconductor layer includes silicon carbide and a first element and is provided on a base body including silicon carbide. The first element includes at least one selected from the group consisting of N, P, and As. The method can include a second process of forming a second semiconductor layer on the first semiconductor layer after the first process. The second semiconductor layer includes silicon carbide and the first element. The method can include a third process of forming a third semiconductor layer on the second semiconductor layer. The third semiconductor layer includes silicon carbide and a second element. The second element includes at least one selected from the group consisting of B, Al, and Ga.Type: GrantFiled: September 10, 2019Date of Patent: October 19, 2021Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Johji Nishio, Chiharu Ota, Ryosuke Iijima
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Publication number: 20210296128Abstract: A semiconductor device according to an embodiment includes: a silicon carbide layer; a silicon oxide layer; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1×1021 cm?3. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region have a peak in the region, a nitrogen concentration at a first position 1 nm away from the peak to the side of the silicon oxide layer is equal to or less than 1×1018 cm?3 and a carbon concentration at the first position is equal to or less than 1×1018 cm3, and a nitrogen concentration at a second position 1 nm away from the peak to the side of the silicon carbide layer is equal to or less than 1×1018 cm?3.Type: ApplicationFiled: August 24, 2020Publication date: September 23, 2021Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tatsuo SHIMIZU, Yukio NAKABAYASHI, Johji NISHIO, Chiharu OTA, Toshihide ITO
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Publication number: 20210296446Abstract: A semiconductor device according to an embodiment includes: a silicon carbide layer; a silicon oxide layer; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1×1021 cm?3. Nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region have a peak in the region, a nitrogen concentration at a position 1 nm away from the peak to the side of the silicon oxide layer is equal to or less than 1×1018 cm?3, and a carbon concentration at the position is equal to or less than 1×1018 cm?3.Type: ApplicationFiled: August 13, 2020Publication date: September 23, 2021Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tatsuo Shimizu, Yukio Nakabayashi, Johji Nishio, Chiharu Ota, Toshihide Ito
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Publication number: 20210217619Abstract: According to one embodiment, a method for manufacturing a silicon carbide base body is disclosed. The method can include preparing a first base body including silicon carbide. The first base body includes a first base body surface tilted with respect to a (0001) plane of the first base body. A first line segment where the first base body surface and the (0001) plane of the first base body intersect is along a [11-20] direction of the first base body. The method can include forming a first layer at the first base body surface. The first layer includes silicon carbide. The method can include removing a portion of the first layer. The first-layer surface is tilted with respect to a (0001) plane of the first layer. A second line segment where the first-layer surface and the (0001) plane of the first layer intersect is along a [?1100] direction.Type: ApplicationFiled: August 27, 2020Publication date: July 15, 2021Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Johji NISHIO, Chiharu OTA
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Patent number: 10998401Abstract: According to one embodiment, a semiconductor device includes a base body including silicon carbide, a first semiconductor region including silicon carbide and a first element, and a second semiconductor region including silicon carbide and the first element. The first semiconductor region includes first and second intermediate regions. A first concentration of the first element in the first intermediate region satisfies a first or a second condition. In the first condition, the first concentration is lower than a second concentration of the first element in the second intermediate region. In the second condition, the first concentration is higher than a third concentration of a second element included in the first intermediate region, the second concentration is higher than a fourth concentration of the second element in the second intermediate region, and a difference between the first and third concentrations is smaller than a difference between the second and fourth concentrations.Type: GrantFiled: September 10, 2019Date of Patent: May 4, 2021Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Johji Nishio, Chiharu Ota, Ryosuke Iijima
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Publication number: 20200251560Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include a first process of causing a stacking fault of a first semiconductor layer to expand. The first semiconductor layer includes silicon carbide and a first element and is provided on a base body including silicon carbide. The first element includes at least one selected from the group consisting of N, P, and As. The method can include a second process of forming a second semiconductor layer on the first semiconductor layer after the first process. The second semiconductor layer includes silicon carbide and the first element. The method can include a third process of forming a third semiconductor layer on the second semiconductor layer. The third semiconductor layer includes silicon carbide and a second element. The second element includes at least one selected from the group consisting of B, Al, and Ga.Type: ApplicationFiled: September 10, 2019Publication date: August 6, 2020Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Johji NISHIO, Chiharu OTA, Ryosuke IIJIMA
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Patent number: 10651280Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first to fourth semiconductor regions, and a first insulating portion. The first semiconductor region includes first to third partial regions. The first partial region is provided between the first electrode and the second electrode. The second partial region is provided between the first and third electrodes. The second semiconductor region includes fourth to sixth partial regions. The fourth partial region is provided between the first partial region and the second electrode. The fifth partial region is provided between the third semiconductor region and at least a portion of the second partial region. The sixth partial region is provided between the third partial region and the third semiconductor region. The fourth semiconductor region is provided between the first and fourth partial regions. The first insulating portion is provided between the second partial region and the third electrode.Type: GrantFiled: August 10, 2018Date of Patent: May 12, 2020Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Chiharu Ota, Tatsunori Sakano, Ryosuke Iijima
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Publication number: 20200127083Abstract: According to one embodiment, a semiconductor device includes a base body including silicon carbide, a first semiconductor region including silicon carbide and a first element, and a second semiconductor region including silicon carbide and the first element. The first semiconductor region includes first and second intermediate regions. A first concentration of the first element in the first intermediate region satisfies a first or a second condition. In the first condition, the first concentration is lower than a second concentration of the first element in the second intermediate region. In the second condition, the first concentration is higher than a third concentration of a second element included in the first intermediate region, the second concentration is higher than a fourth concentration of the second element in the second intermediate region, and a difference between the first and third concentrations is smaller than a difference between the second and fourth concentrations.Type: ApplicationFiled: September 10, 2019Publication date: April 23, 2020Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Johji NISHIO, Chiharu OTA, Ryosuke IIJIMA
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Patent number: 10629687Abstract: According to one embodiment, a semiconductor device includes a first element. The first element includes a first electrode, a second electrode and first to fourth semiconductor regions. The second electrode includes a first conductive region and a second conductive region. The first semiconductor region is provided between the first electrode and the first conductive region and between the first electrode and the second conductive region. The second semiconductor region includes a first partial region and a second partial region. The first partial region is provided between the first electrode and the first conductive region. The second partial region is provided between the first electrode and the second conductive region. The third semiconductor region is provided between the second partial region and the second conductive region. The fourth semiconductor region is provided between the third semiconductor region and the second conductive region.Type: GrantFiled: August 10, 2018Date of Patent: April 21, 2020Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Chiharu Ota, Tatsunori Sakano, Tatsuo Shimizu, Ryosuke Iijima
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Publication number: 20190273135Abstract: According to one embodiment, a semiconductor device includes a first element. The first element includes a first electrode, a second electrode and first to fourth semiconductor regions. The second electrode includes a first conductive region and a second conductive region. The first semiconductor region is provided between the first electrode and the first conductive region and between the first electrode and the second conductive region. The second semiconductor region includes a first partial region and a second partial region. The first partial region is provided between the first electrode and the first conductive region. The second partial region is provided between the first electrode and the second conductive region. The third semiconductor region is provided between the second partial region and the second conductive region. The fourth semiconductor region is provided between the third semiconductor region and the second conductive region.Type: ApplicationFiled: August 10, 2018Publication date: September 5, 2019Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Chiharu Ota, Tatsunori Sakano, Tatsuo Shimizu, Ryosuke Iijima
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Publication number: 20190273134Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first to fourth semiconductor regions, and a first insulating portion. The first semiconductor region includes first to third partial regions. The first partial region is provided between the first electrode and the second electrode. The second partial region is provided between the first and third electrodes. The second semiconductor region includes fourth to sixth partial regions. The fourth partial region is provided between the first partial region and the second electrode. The fifth partial region is provided between the third semiconductor region and at least a portion of the second partial region. The sixth partial region is provided between the third partial region and the third semiconductor region. The fourth semiconductor region is provided between the first and fourth partial regions. The first insulating portion is provided between the second partial region and the third electrode.Type: ApplicationFiled: August 10, 2018Publication date: September 5, 2019Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Chiharu Ota, Tatsunori Sakano, Ryosuke Iijima
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Patent number: 10079282Abstract: A semiconductor device according to an embodiment includes an i-type or a p-type first diamond semiconductor layer, an n-type second diamond semiconductor layer provided on the first diamond semiconductor layer, a mesa structure and an n-type first diamond semiconductor region provided on the side surface. The mesa structure includes the first diamond semiconductor layer, the second diamond semiconductor layer, a top surface with a plane orientation of ±10 degrees or less from a {100} plane, and a side surface inclined by 20 to 90 degrees with respect to a direction of <011>±20 degrees from the {100} plane. The first diamond semiconductor region is in contact with the second diamond semiconductor layer and has an n-type impurity concentration lower than an n-type impurity concentration of the second diamond semiconductor layer.Type: GrantFiled: August 29, 2014Date of Patent: September 18, 2018Assignee: Kabushiki Kaisha ToshibaInventors: Mariko Suzuki, Tadashi Sakai, Chiharu Ota, Kazuto Takao, Takashi Shinohe
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Publication number: 20170365664Abstract: A semiconductor device according to an embodiment, includes: a silicon carbide layer; a gate electrode; and a gate insulating layer, the gate electrode including a p-type silicon carbide region containing aluminum, the gate insulating layer having a first region and a second region, the first region including a silicon oxide or a silicon oxynitride, the second region being positioned between the first region and the gate electrode, the second region including an oxide containing aluminum.Type: ApplicationFiled: February 23, 2017Publication date: December 21, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Ryosuke IIJIMA, Tatsuo SHIMIZU, Chiharu OTA
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Patent number: 9653553Abstract: A semiconductor substrate of an embodiment includes a SiC layer having a surface inclined in a <11-20> direction plus or minus 5° from a {0001} face at an off angle of 0° to 10°. Area density of threading edge dislocation clusters in the SiC layer is 18.8 cm?2 or less, each of the threading edge dislocation clusters includes a plurality of threading edge dislocations on the surface, the threading edge dislocations included in each of the threading edge dislocation clusters exist in a region that extends in a [1-100] direction plus or minus 5° and has a width of 30 ?m or less, each of the threading edge dislocation clusters includes at least three threading edge dislocations adjacent at an interval of 30 ?m or less, and an interval of adjacent threading edge dislocations in each of the threading edge dislocation clusters is 70 ?m or less.Type: GrantFiled: February 29, 2016Date of Patent: May 16, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Chiharu Ota, Johji Nishio, Kazuto Takao
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Patent number: 9559172Abstract: A semiconductor device of an embodiment includes a p-type SiC impurity region containing a p-type impurity and an n-type impurity. Where the p-type impurity is an element A and the n-type impurity is an element D, the element A and the element D form a combination of Al (aluminum), Ga (gallium), or In (indium) and N (nitrogen), and/or a combination of B (boron) and P (phosphorus). The ratio of the concentration of the element D to the concentration of the element A in the above combination is higher than 0.33 but lower than 0.995, and the concentration of the element A forming part of the above combination is not lower than 1×1018 cm?3 and not higher than 1×1022 cm?3.Type: GrantFiled: March 12, 2014Date of Patent: January 31, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuo Shimizu, Takashi Shinohe, Johji Nishio, Chiharu Ota
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Patent number: 9484415Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, and a third semiconductor region. The first semiconductor region includes silicon carbide. A conductivity type of the first semiconductor region is a first conductivity type. The second semiconductor region includes silicon carbide. A conductivity type of the second semiconductor region is a second conductivity type. The third semiconductor region includes silicon carbide. A conductivity type of the third semiconductor is the second conductivity type. The third semiconductor region is provided between the first semiconductor region and the second semiconductor region. As viewed in a direction connecting the first semiconductor region and the second semiconductor region, an area of an overlapping region of the second semiconductor region and the third semiconductor region is smaller than an area of an overlapping region of the first semiconductor region and the second semiconductor region.Type: GrantFiled: August 26, 2014Date of Patent: November 1, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Chiharu Ota, Kazuto Takao, Johji Nishio, Takashi Shinohe
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Publication number: 20160268381Abstract: A semiconductor substrate of an embodiment includes a SiC layer having a surface inclined in a <11-20> direction plus or minus 5° from a {0001} face at an off angle of 0° to 10°. Area density of threading edge dislocation clusters in the SiC layer is 18.8 cm?2 or less, each of the threading edge dislocation clusters includes a plurality of threading edge dislocations on the surface, the threading edge dislocations included in each of the threading edge dislocation clusters exist in a region that extends in a [1-100] direction plus or minus 5° and has a width of 30 ?m or less, each of the threading edge dislocation clusters includes at least three threading edge dislocations adjacent at an interval of 30 ?m or less, and an interval of adjacent threading edge dislocations in each of the threading edge dislocation clusters is 70 ?m or less.Type: ApplicationFiled: February 29, 2016Publication date: September 15, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Chiharu OTA, Johji Nishio, Kazuto Takao