Patents by Inventor Chiharu Ota

Chiharu Ota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120056196
    Abstract: A semiconductor device according to an embodiment includes a first-conductive-type semiconductor substrate; a first-conductive-type first semiconductor layer formed on the semiconductor substrate, and having an impurity concentration lower than that of the semiconductor substrate; a second-conductive-type second semiconductor layer epitaxially formed on the first semiconductor layer; and a second-conductive-type third semiconductor layer epitaxially formed on the second semiconductor layer, and having an impurity concentration higher than that of the second semiconductor layer. The semiconductor device also includes a recess formed in the third semiconductor layer, and at least a corner portion of a side face and a bottom surface is located in the second semiconductor layer.
    Type: Application
    Filed: February 24, 2011
    Publication date: March 8, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Chiharu Ota, Takashi Shinohe, Makoto Mizukami, Johji Nishio
  • Publication number: 20120056195
    Abstract: One embodiment of a semiconductor device includes: a silicon carbide substrate including first and second principal surfaces; a first-conductive-type silicon carbide layer on the first principal surface; a second-conductive-type first silicon carbide region at a surface of the first silicon carbide layer; a first-conductive-type second silicon carbide region at the surface of the first silicon carbide region; a second-conductive-type third silicon carbide region at the surface of the first silicon carbide region; a second-conductive-type fourth silicon carbide region formed between the first silicon carbide region and the second silicon carbide region, and having an impurity concentration higher than that of the first silicon carbide region; a gate insulator; a gate electrode formed on the gate insulator; an inter-layer insulator; a first electrode connected to the second silicon carbide region and the third silicon carbide region; and a second electrode on the second principal surface.
    Type: Application
    Filed: February 24, 2011
    Publication date: March 8, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Kono, Takashi Shinohe, Chiharu Ota, Makoto Mizukami, Takuma Suzuki, Johji Nishio
  • Publication number: 20120056198
    Abstract: A semiconductor device according to an embodiment includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a first semiconductor region of a second conductivity type, a second semiconductor region of the second conductivity type, a first electrode and a second electrode. The first semiconductor region is formed on at least a part of the first semiconductor layer formed on the semiconductor substrate. The second semiconductor region is formed on another part of the first semiconductor layer to reach an inside of the first semiconductor layer and having an impurity concentration higher than that of the first semiconductor region. The first electrode is formed on the second semiconductor region and a third semiconductor regions formed in a part of the first semiconductor region. The second electrode is formed to be in contact with a rear surface of the semiconductor substrate.
    Type: Application
    Filed: March 2, 2011
    Publication date: March 8, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Chiharu OTA, Hiroshi Kono, Kazuto Takao, Takashi Shinohe
  • Patent number: 8012837
    Abstract: A method of manufacturing a semiconductor device capable of realizing a high yield of a large-scale semiconductor device even when a silicon carbide semiconductor including a defect is used is provided. The method of manufacturing a semiconductor device includes: a step of epitaxially growing a silicon carbide semiconductor layer on a silicon carbide semiconductor substrate; a step of polishing a surface of the silicon carbide semiconductor layer; a step of ion-implanting impurities into the silicon carbide semiconductor layer after the step of polishing; a step of performing heat treatment to activate the impurities; a step of forming a first thermal oxide film on the surface of the silicon carbide semiconductor layer after the step of performing heat treatment; a step of chemically removing the first thermal oxide film; and a step of forming an electrode layer on the silicon carbide semiconductor film.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: September 6, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Johji Nishio, Chiharu Ota, Takuma Suzuki, Hiroshi Kono, Makoto Mizukami, Takashi Shinohe
  • Patent number: 7977210
    Abstract: A semiconductor substrate includes a silicon carbide substrate having a first impurity concentration, a first silicon carbide layer formed on the silicon carbide substrate and having a second impurity concentration, and a second silicon carbide layer of a first conductivity type formed on the first silicon carbide layer and having a third impurity concentration, wherein the second impurity concentration is higher the an either the first impurity concentration or the third impurity concentration.
    Type: Grant
    Filed: November 25, 2008
    Date of Patent: July 12, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chiharu Ota, Johji Nishio, Takashi Shinohe
  • Patent number: 7947988
    Abstract: A semiconductor device includes an SiC substrate, a first SiC layer of first conductivity provided on the substrate, a second SiC layer of second conductivity provided on the first SiC layer, first and second SiC regions provided in the second SiC layer, facing each other and having the same depth, a third SiC region extending through the first SiC region and reaching the first SiC layer, a gate insulator formed on the first and second SiC regions and the second SiC layer interposed therebetween, a gate electrode formed on the gate insulator, a first contact of first conductivity formed on the second SiC region, a second contact of second conductivity formed on the second SiC region, reaching the second SiC layer through the second SiC region, and a top electrode formed on the first and second contacts, and a bottom electrode formed on a back surface of the substrate.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: May 24, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Kono, Takashi Shinohe, Chiharu Ota, Johji Nishio
  • Publication number: 20110059597
    Abstract: A method of manufacturing a semiconductor device capable of realizing a high yield of a large-scale semiconductor device even when a silicon carbide semiconductor including a defect is used is provided. The method of manufacturing a semiconductor device includes: a step of epitaxially growing a silicon carbide semiconductor layer on a silicon carbide semiconductor substrate; a step of polishing a surface of the silicon carbide semiconductor layer; a step of ion-implanting impurities into the silicon carbide semiconductor layer after the step of polishing; a step of performing heat treatment to activate the impurities; a step of forming a first thermal oxide film on the surface of the silicon carbide semiconductor layer after the step of performing heat treatment; a step of chemically removing the first thermal oxide film; and a step of forming an electrode layer on the silicon carbide semiconductor film.
    Type: Application
    Filed: March 3, 2010
    Publication date: March 10, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Johji Nishio, Chiharu Ota, Takuma Suzuki, Hiroshi Kono, Makoto Mizukami, Takashi Shinohe
  • Patent number: 7777292
    Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type having a top surface and a bottom surface, a semiconductor layer of a first conductivity type formed on the top surface of the semiconductor substrate, and having an active region and an edge termination region surrounding the active region, a first semiconductor region of a second conductivity type formed in the edge termination region adjacent to an edge of the active region, a second semiconductor region of a second conductivity type buried in the edge termination region in a sheet shape or a mesh shape substantially in parallel with a surface of the semiconductor layer, a first electrode formed on the active region of the semiconductor layer and a part of the first semiconductor region, and a second electrode formed on the bottom surface of the semiconductor substrate.
    Type: Grant
    Filed: June 25, 2007
    Date of Patent: August 17, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chiharu Ota, Johji Nishio, Tetsuo Hatakeyama, Takashi Shinohe
  • Publication number: 20090134405
    Abstract: A semiconductor substrate includes a silicon carbide substrate having a first impurity concentration, a first silicon carbide layer formed on the silicon carbide substrate and having a second impurity concentration, and a second silicon carbide layer of a first conductivity type formed on the first silicon carbide layer and having a third impurity concentration, wherein the second impurity concentration is higher than either the first impurity concentration or the third impurity concentration.
    Type: Application
    Filed: November 25, 2008
    Publication date: May 28, 2009
    Inventors: Chiharu OTA, Johji Nishio, Takashi Shinohe
  • Patent number: 7532479
    Abstract: In a spread illuminating apparatus including: an LED at a side surface of a light conductor plate; and an FPC having a land formed on a side thereof for mounting the LED, throughholes are formed at the land, and solder is contained at least partly in each of the throughholes, whereby the LED can be mounted solidly on the FPC with a high precision in height position from the FPC, and at the same time the heat emitted from the LED can be efficiently conducted to a conductive pattern at the rear side of the FPC through an electrode terminal of the LED and the throughholes filled with the solder composed of a metallic material having a high heat conductance.
    Type: Grant
    Filed: February 20, 2007
    Date of Patent: May 12, 2009
    Assignee: Minebea Co., Ltd.
    Inventors: Yasuo Ohno, Chiharu Ota
  • Publication number: 20090078942
    Abstract: A semiconductor device includes an SiC substrate, a first SiC layer of first conductivity provided on the substrate, a second SiC layer of second conductivity provided on the first SiC layer, first and second SiC regions provided in the second SiC layer, facing each other and having the same depth, a third SiC region extending through the first SiC region and reaching the first SiC layer, a gate insulator formed on the first and second SiC regions and the second SiC layer interposed therebetween, a gate electrode formed on the gate insulator, a first contact of first conductivity formed on the second SiC region, a second contact of second conductivity formed on the second SiC region, reaching the second SiC layer through the second SiC region, and a top electrode formed on the first and second contacts, and a bottom electrode formed on a back surface of the substrate.
    Type: Application
    Filed: August 28, 2008
    Publication date: March 26, 2009
    Inventors: Hiroshi Kono, Takashi Shinohe, Chiharu Ota, Johji Nishio
  • Patent number: 7508045
    Abstract: A semiconductor device includes a first-conductivity-type SiC substrate, a first-conductivity-type SiC semiconductor layer formed on the substrate, whose impurity concentration is lower than that of the substrate, a first electrode formed on the semiconductor layer and forming a Schottky junction with the semiconductor layer, a barrier height of the Schottky junction being 1 eV or less, plural second-conductivity-type junction barriers formed to contact the first electrode and each having a depth d1 from an upper surface of the semiconductor layer, a width w, and a space s between adjacent ones of the junction barriers, a second-conductivity-type edge termination region formed outside the junction barriers to contact the first electrode and having a depth d2 from the upper surface of the semiconductor layer, and a second electrode formed on the second surface of the substrate, wherein following relations are satisfied d1/d2?1, s/d1?0.6, and s/(w+s)?0.33.
    Type: Grant
    Filed: July 12, 2007
    Date of Patent: March 24, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Johji Nishio, Takuma Suzuki, Chiharu Ota, Takashi Shinohe
  • Patent number: 7420158
    Abstract: In a spread illuminating apparatus, at least one point light source is disposed at an end wall of an outer frame member, and a subassembly is constituted by a light conductor plate and an inner frame member via first joint means. The subassembly has interface surfaces to make contact with the end wall of the outer frame member, a light inlet face of the light conductor plate is positioned to recede from the interface surface by a predetermined dimension, the first joint means each includes a elastic member to press the light conductor plate toward the interface surfaces, and the subassembly is jointed to the outer frame member via second joint means each constituted by an elastic member to press the interface surfaces toward the end wall of the outer frame member.
    Type: Grant
    Filed: May 4, 2007
    Date of Patent: September 2, 2008
    Assignee: Minebea Co., Ltd.
    Inventors: Yasuo Ohno, Katsumi Nagata, Masahisa Nishio, Chiharu Ota
  • Publication number: 20080169475
    Abstract: A semiconductor device includes a first-conductivity-type SiC substrate, a first-conductivity-type SiC semiconductor layer formed on the substrate, whose impurity concentration is lower than that of the substrate, a first electrode formed on the semiconductor layer and forming a Schottky junction with the semiconductor layer, a barrier height of the Schottky junction being 1 eV or less, plural second-conductivity-type junction barriers formed to contact the first electrode and each having a depth d1 from an upper surface of the semiconductor layer, a width w, and a space s between adjacent ones of the junction barriers, a second-conductivity-type edge termination region formed outside the junction barriers to contact the first electrode and having a depth d2 from the upper surface of the semiconductor layer, and a second electrode formed on the second surface of the substrate, wherein following relations are satisfied d1/d2?1, s/d1?0.6, and s/(w+s)?0.33.
    Type: Application
    Filed: July 12, 2007
    Publication date: July 17, 2008
    Inventors: Johji Nishio, Takuma Suzuki, Chiharu Ota, Takashi Shinohe
  • Publication number: 20080001159
    Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type having a top surface and a bottom surface, a semiconductor layer of a first conductivity type formed on the top surface of the semiconductor substrate, and having an active region and an edge termination region surrounding the active region, a first semiconductor region of a second conductivity type formed in the edge termination region adjacent to an edge of the active region, a second semiconductor region of a second conductivity type buried in the edge termination region in a sheet shape or a mesh shape substantially in parallel with a surface of the semiconductor layer, a first electrode formed on the active region of the semiconductor layer and a part of the first semiconductor region, and a second electrode formed on the bottom surface of the semiconductor substrate.
    Type: Application
    Filed: June 25, 2007
    Publication date: January 3, 2008
    Inventors: Chiharu Ota, Johji Nishio, Tetsuo Hatakeyama, Takashi Shinohe
  • Publication number: 20070267564
    Abstract: In a spread illuminating apparatus, at least one point light source is disposed at an end wall of an outer frame member, and a subassembly is constituted by a light conductor plate and an inner frame member via first joint means. The subassembly has interface surfaces to make contact with the end wall of the outer frame member, a light inlet face of the light conductor plate is positioned to recede from the interface surface by a predetermined dimension, the first joint means each includes a elastic member to press the light conductor plate toward the interface surfaces, and the subassembly is jointed to the outer frame member via second joint means each constituted by an elastic member to press the interface surfaces toward the end wall of the outer frame member.
    Type: Application
    Filed: May 4, 2007
    Publication date: November 22, 2007
    Applicant: MINEBEA CO., LTD.
    Inventors: Yasuo Ohno, Katsumi Nagata, Masahisa Nishio, Chiharu Ota
  • Publication number: 20070201247
    Abstract: In a spread illuminating apparatus including: an LED at a side surface of a light conductor plate; and an FPC having a land formed on a side thereof for mounting the LED, throughholes are formed at the land, and solder is contained at least partly in each of the throughholes, whereby the LED can be mounted solidly on the FPC with a high precision in height position from the FPC, and at the same time the heat emitted from the LED can be efficiently conducted to a conductive pattern at the rear side of the FPC through an electrode terminal of the LED and the throughholes filled with the solder composed of a metallic material having a high heat conductance.
    Type: Application
    Filed: February 20, 2007
    Publication date: August 30, 2007
    Applicant: MINEBEA CO., LTD.
    Inventors: Yasuo Ohno, Chiharu Ota