Abstract: A semiconductor device of an embodiment includes: an n-type first SiC epitaxial layer; a p-type second SiC epitaxial layer provided on the first SiC epitaxial layer and contains a p-type impurity and an n-type impurity, the p-type impurity being an element A, the n-type impurity being an element D, the element A and the element D forming a combination of Al, Ga, or In and N, and/or a combination of B and P, the ratio of the concentration of the element D to the concentration of the element A in the combination(s) being higher than 0.33 but lower than 1.0; n-type first and second SiC regions provided in the surface of the second SiC epitaxial layer; a gate insulating film; a gate electrode; a first electrode provided on the second SiC region; and a second electrode provided on the opposite side from the first electrode.

Abstract: A semiconductor device of an embodiment includes: an n-type first SiC epitaxial layer; a p-type second SiC epitaxial layer on the first SiC epitaxial layer containing a p-type impurity and an n-type impurity, the p-type impurity being an element A, the n-type impurity being an element D, the element A and the element D forming a combination of Al, Ga, or In and N, and/or a combination of B and P, the ratio of the concentration of the element D to the element A being higher than 0.33 but lower than 1.0; a surface region at the surface of the second SiC epitaxial layer containing the element A at a lower concentration than in the second SiC epitaxial layer, the ratio being higher than in the second SiC epitaxial layer; n-type first and second SiC regions; a gate insulating film; a gate electrode; a first electrode; and a second electrode.

Abstract: A semiconductor device of an embodiment includes an n-type SiC substrate, an n-type SiC layer formed on the SiC substrate; a p-type first SiC region formed in the surface of the SiC layer and contains a p-type impurity and an n-type impurity, the p-type impurity being an element A, the n-type impurity being an element D, the element A and the element D being a combination of Al, Ga, or In and N, and/or a combination of B and P, the ratio of the concentration of the element D to the concentration of the element A in the combination(s) being higher than 0.33 but lower than 0.995, the concentration of the element A forming part of the combination(s) being not lower than 1×1017 cm?3 and not higher than 1×1022 cm?3, a first electrode, and a second electrode.

Abstract: An SiC epitaxial wafer of an embodiment includes, an SiC substrate, and a p-type first SiC epitaxial layer that is formed on the SiC substrate and contains a p-type impurity and an n-type impurity. An element A and an element D being a combination of Al (aluminum), Ga (gallium), or In (indium) and N (nitrogen), and/or a combination of B (boron) and P (phosphorus) when the p-type impurity is the element A and the n-type impurity is the element D. The ratio of the concentration of the element D to the concentration of the element A in the combination(s) is higher than 0.33 but lower than 1.0.

Abstract: A semiconductor device according to an embodiment includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a first semiconductor region of a second conductivity type, a second semiconductor region of the second conductivity type, a first electrode and a second electrode. The first semiconductor region is formed on at least a part of the first semiconductor layer formed on the semiconductor substrate. The second semiconductor region is formed on another part of the first semiconductor layer to reach an inside of the first semiconductor layer and having an impurity concentration higher than that of the first semiconductor region. The first electrode is formed on the second semiconductor region and a third semiconductor regions formed in a part of the first semiconductor region. The second electrode is formed to be in contact with a rear surface of the semiconductor substrate.

Abstract: A semiconductor device according to an embodiment includes a first-conductive-type semiconductor substrate; a first-conductive-type first semiconductor layer formed on the semiconductor substrate, and having an impurity concentration lower than that of the semiconductor substrate; a second-conductive-type second semiconductor layer epitaxially formed on the first semiconductor layer; and a second-conductive-type third semiconductor layer epitaxially formed on the second semiconductor layer, and having an impurity concentration higher than that of the second semiconductor layer. The semiconductor device also includes a recess formed in the third semiconductor layer, and at least a corner portion of a side face and a bottom surface is located in the second semiconductor layer.

Abstract: A semiconductor device of an embodiment includes an n-type SiC substrate, an n-type SiC layer formed on the SiC substrate; a p-type first SiC region formed in the surface of the SiC layer and contains a p-type impurity and an n-type impurity, the p-type impurity being an element A, the n-type impurity being an element D, the element A and the element D being a combination of Al, Ga, or In and N, and/or a combination of B and P, the ratio of the concentration of the element D to the concentration of the element A in the combination(s) being higher than 0.33 but lower than 0.995, the concentration of the element A forming part of the combination(s) being not lower than 1×1017 cm?3 and not higher than 1×1022 cm?3, a first electrode, and a second electrode.

Abstract: A vapor phase growth apparatus of an embodiment includes a reaction chamber, a first gas supply channel that supplies a Si source gas to the reaction chamber, a second gas supply channel that supplies a C source gas to the reaction chamber, a third gas supply channel that supplies an n-type impurity source gas to the reaction chamber, a fourth gas supply channel that supplies a p-type impurity source gas to the reaction chamber, and a control unit that controls the amounts of the n-type impurity and p-type impurity source gases at a predetermined ratio, and introduces the n-type impurity and p-type impurity source gases into the reaction chamber. Where the p-type impurity is an element A and the n-type impurity is an element D, the element A and the element D form a combination of Al, Ga, or In and N, and/or a combination of B and P.

Abstract: According to one embodiment, a rectifier includes a rectifying device, a control element and a controller. The control element is serially connected to the rectifying device. The control element has a resistance value that changes according to a control signal. The controller generates the control signal according to a change in a current flowing in the rectifying device.

Abstract: A semiconductor device of an embodiment includes, an n-type SiC substrate that has first and second faces, and contains a p-type impurity and an n-type impurity, the p-type impurity being an element A, the n-type impurity being an element D, the element A and the element D being a combination of Al (aluminum), Ga (gallium), or In (indium) and N (nitrogen), and/or a combination of B (boron) and P (phosphorus), the ratio of the concentration of the element A to the concentration of the element D in the combination(s) being higher than 0.40 but lower than 0.95, the concentration of the element D forming the combination(s) being not lower than 1×1018 cm?3 and not higher than 1×1022 cm?3, an SiC layer formed on the first face, a first electrode formed on the first face side, and a second electrode formed on the second face.

Abstract: An SiC epitaxial wafer of an embodiment includes, an SiC substrate, and a p-type first SiC epitaxial layer that is formed on the SiC substrate and contains a p-type impurity and an n-type impurity. An element A and an element D being a combination of Al (aluminum), Ga (gallium), or In (indium) and N (nitrogen), and/or a combination of B (boron) and P (phosphorus) when the p-type impurity is the element A and the n-type impurity is the element D. The ratio of the concentration of the element D to the concentration of the element A in the combination(s) is higher than 0.33 but lower than 1.0.

Abstract: A semiconductor device of an embodiment includes an n-type SiC impurity region containing a p-type impurity and an n-type impurity. Where the p-type impurity is an element A and the n-type impurity is an element D, the element A and the element D form a combination of Al (aluminum), Ga (gallium), or In (indium) and N (nitrogen), and/or a combination of B (boron) and P (phosphorus). The ratio of the concentration of the element A to the concentration of the element D in the above combination is higher than 0.40 but lower than 0.95, and the concentration of the element D forming the above combination is not lower than 1×1018 cm?3 and not higher than 1×1022 cm?3.

Abstract: A semiconductor device of an embodiment includes a p-type SiC impurity region containing a p-type impurity and an n-type impurity. Where the p-type impurity is an element A and the n-type impurity is an element D, the element A and the element D form a combination of Al (aluminum), Ga (gallium), or In (indium) and N (nitrogen), and/or a combination of B (boron) and P (phosphorus). The ratio of the concentration of the element D to the concentration of the element A in the above combination is higher than 0.33 but lower than 0.995, and the concentration of the element A forming part of the above combination is not lower than 1×1018 cm?3 and not higher than 1×1022 cm?3.

Abstract: According to one embodiment, a semiconductor substrate includes a substrate and a semiconductor layer. The substrate has a first surface and containing a silicon carbide. The semiconductor layer is provided on the first surface. The semiconductor layer has a thickness of H centimeters in a perpendicular direction to the first surface. The semiconductor layer contains an epitaxially grown silicon carbide with an off angle ? provided relative to a (0001) face of the substrate. The semiconductor layer includes k pieces of basal plane dislocation per one square centimeter viewed in the perpendicular direction. When S=(½)×H2/(tan ?(sin ?×tan 30°)) square centimeters, k×S<0.075 square centimeters is satisfied.

Abstract: A semiconductor device includes a first-conductivity-type semiconductor substrate; a first-conductivity-type first semiconductor layer formed on the semiconductor substrate, and having an impurity concentration lower than that of the semiconductor substrate; a second-conductivity-type second semiconductor layer epitaxially formed on the first semiconductor layer; a second-conductivity-type third semiconductor layer epitaxially formed on the second semiconductor layer, and having an impurity concentration higher than that of the second semiconductor layer; a recess formed in the third semiconductor layer, at least a corner portion of a side face and a bottom surface of the recess being located in the second semiconductor layer; a first electrode in contact with the third semiconductor layer; a second electrode connected to the first electrode and in contact with the second semiconductor layer at the bottom surface of the recess; and a third electrode in contact with a lower surface of the semiconductor substra

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type made of silicon carbide; and a second semiconductor layer of a second conductivity type made of silicon carbide, placed in junction with the first semiconductor layer, and containing an electrically inactive element.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a first electrode and a heat generation portion. The first semiconductor region includes n-type silicon carbide. The second semiconductor region is provided on a portion of the first semiconductor region. The second semiconductor region includes p-type silicon carbide. The first electrode provided on the first semiconductor region and the second semiconductor region. The heat generation portion is provided on the second semiconductor region.

Abstract: A method of manufacturing a semiconductor device of an embodiment includes: preparing a silicon carbide substrate of a hexagonal system; implanting ions into the silicon carbide substrate; forming, by epitaxial growth, a silicon carbide film on the silicon carbide substrate into which the ions have been implanted; and forming a pn junction region in the silicon carbide film.

Abstract: According to one embodiment, a semiconductor device, includes: a first semiconductor region of a first conductivity type; a second semiconductor region provided on the first semiconductor region, an impurity concentration of the second semiconductor region being lower than an impurity concentration of the first semiconductor region; a third semiconductor region of a second conductivity type provided on the second semiconductor region; and a fourth semiconductor region provided on the third semiconductor region or in a portion of the third semiconductor region. A lattice strain of the fourth semiconductor region is greater than a lattice strain of the third semiconductor region.

Abstract: A method of manufacturing a semiconductor device of an embodiment includes: preparing a silicon carbide substrate of a hexagonal system; implanting ions into the silicon carbide substrate; forming, by epitaxial growth, a silicon carbide film on the silicon carbide substrate into which the ions have been implanted; and forming a pn junction region in the silicon carbide film.