Patents by Inventor Chih-Cheng Liu

Chih-Cheng Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250147417
    Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate. A first precursor and a second precursor are combined. The first precursor is an organometallic having a formula: MaRbXc, where M is one or more of Sn, Bi, Sb, In, and Te, R is one or more of a C7-C11 aralkyl group, a C3-C10 cycloalkyl group, a C2-C10 alkoxy group, and a C2-C10 alkylamino group, X is one or more of a halogen, a sulfonate group, and an alkylamino group, and 1?a?2, b?1, c?1, and b+c?4, and the second precursor is one or more of water, an amine, a borane, and a phosphine. The photoresist layer is selectively exposed to actinic radiation to form a latent pattern. The latent pattern is developed by applying a developer to the selectively exposed photoresist layer.
    Type: Application
    Filed: December 30, 2024
    Publication date: May 8, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Cheng LIU, Ming-Hui WENG, Jr-Hung LI, Yahru CHENG, Chi-Ming YANG, Tze-Liang LEE, Ching-Yu CHANG
  • Patent number: 12288759
    Abstract: A semiconductor structure includes: a substrate, a conductive pattern layer, a support layer and a re-distribution layer. The conductive pattern layer is arranged on the substrate. The support layer covers the conductive pattern layer and is provided with a via hole. The re-distribution layer is arranged on the support, and the re-distribution layer includes a test pad at least located in the via hole. The test pad includes a plurality of test contact portions and a plurality of recesses that are arranged alternately and connected mutually, and the recess is in corresponding contact with a portion of the conductive pattern layer in the via hole.
    Type: Grant
    Filed: April 5, 2022
    Date of Patent: April 29, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Chih-Cheng Liu
  • Publication number: 20250118569
    Abstract: A method includes following steps. A target layer is formed over a substrate. A first hard mask layer is formed over the target layer by a plasma generated using a first radio frequency generator and a second radio frequency generator. The first radio frequency generator and the second radio frequency generator have different powers. A second hard mask layer is formed over the first hard mask layer by a plasma generated using the first radio frequency generator without using the second radio frequency generator. A photoresist layer is formed over the second hard mask layer. The photoresist layer is exposed. The photoresist layer is developed. The first hard mask layer and the second hard mask layer are patterned using the photoresist layer as an etch mask. The target layer is patterned using the first hard mask layer and the second hard mask layer as an etch mask.
    Type: Application
    Filed: October 5, 2023
    Publication date: April 10, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Cheng LIU, Wei-Zhong CHEN, Chi-Ming YANG, Jr-Hung LI, Yung-Cheng LU
  • Patent number: 12272554
    Abstract: A method of manufacturing semiconductor device includes forming a multilayer photoresist structure including a metal-containing photoresist over a substrate. The multilayer photoresist structure includes two or more metal-containing photoresist layers having different physical parameters. The metal-containing photoresist is a reaction product of a first precursor and a second precursor, and each layer of the multilayer photoresist structure is formed using different photoresist layer formation parameters. The different photoresist layer formation parameters are one or more selected from the group consisting of the first precursor, an amount of the first precursor, the second precursor, an amount of the second precursor, a length of time each photoresist layer formation operation, and heating conditions of the photoresist layers.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: April 8, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jia-Lin Wei, Ming-Hui Weng, Chih-Cheng Liu, Yi-Chen Kuo, Yen-Yu Chen, Yahru Cheng, Jr-Hung Li, Ching-Yu Chang, Tze-Liang Lee, Chi-Ming Yang
  • Patent number: 12271113
    Abstract: Method of manufacturing semiconductor device includes forming photoresist layer over substrate. Forming photoresist layer includes combining first precursor and second precursor in vapor state to form photoresist material, wherein first precursor is organometallic having formula: MaRbXc, where M at least one of Sn, Bi, Sb, In, Te, Ti, Zr, Hf, V, Co, Mo, W, Al, Ga, Si, Ge, P, As, Y, La, Ce, Lu; R is substituted or unsubstituted alkyl, alkenyl, carboxylate group; X is halide or sulfonate group; and 1?a?2, b?1, c?1, and b+c?5. Second precursor is at least one of an amine, a borane, a phosphine. Forming photoresist layer includes depositing photoresist material over the substrate. The photoresist layer is selectively exposed to actinic radiation to form latent pattern, and the latent pattern is developed by applying developer to selectively exposed photoresist layer to form pattern.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: April 8, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Cheng Liu, Yi-Chen Kuo, Jia-Lin Wei, Ming-Hui Weng, Yen-Yu Chen, Jr-Hung Li, Yahru Cheng, Chi-Ming Yang, Tze-Liang Lee, Ching-Yu Chang
  • Publication number: 20250096162
    Abstract: A semiconductor structure and a manufacturing method therefor are disclosed. The semiconductor structure includes an interposer, where the interposer includes a deep trench capacitor array and an isolation structure. The deep trench capacitor array includes multiple deep trench capacitors, and the isolation structure at least partially surrounds a deep trench capacitor on the outmost edge side of the deep trench capacitor array.
    Type: Application
    Filed: November 28, 2024
    Publication date: March 20, 2025
    Inventors: You FU, Shuangshuang WU, TZUNG-HAN LEE, CHIH-CHENG LIU, Xiaolong CHEN
  • Patent number: 12255125
    Abstract: A semiconductor structure includes a substrate, a via, a conductive pillar, and a core layer. The via is located in the substrate. The conductive pillar is located in the via, and the conductive pillar is provided with a groove extended inwards from an upper surface of the conductive pillar. The core layer is located in the groove, a Young modulus of the core layer is less than that of the conductive pillar.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: March 18, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Chih-Cheng Liu
  • Publication number: 20250070062
    Abstract: Provided are a semiconductor interconnection structure, which includes a base, multiple independent conductive pillars, and a first conductive connection pad. The base has a first surface and a second surface. The multiple independent conductive pillars are disposed in the base. The first conductive connection pad is disposed on the first surface of the base and includes a mesh structure, and the mesh structure includes multiple first nodes. Each of the first nodes is connected to a first end of one or first ends of more of the conductive pillars, or a first end of each of the conductive pillars is connected to one or more of the first nodes. First ends of all the conductive pillars are interconnected through the first conductive connection pad. The semiconductor interconnection structure has good heat dissipation performance and mechanical performance.
    Type: Application
    Filed: November 14, 2024
    Publication date: February 27, 2025
    Inventor: Chih-Cheng LIU
  • Patent number: 12222643
    Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate. A first precursor and a second precursor are combined. The first precursor is an organometallic having a formula: MaRbXc, where M is one or more of Sn, Bi, Sb, In, and Te, R is one or more of a C7-C11 aralkyl group, a C3-C10 cycloalkyl group, a C2-C10 alkoxy group, and a C2-C10 alkylamino group, X is one or more of a halogen, a sulfonate group, and an alkylamino group, and 1?a?2, b?1, c?1, and b+c?4, and the second precursor is one or more of water, an amine, a borane, and a phosphine. The photoresist layer is selectively exposed to actinic radiation to form a latent pattern. The latent pattern is developed by applying a developer to the selectively exposed photoresist layer.
    Type: Grant
    Filed: October 22, 2022
    Date of Patent: February 11, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Cheng Liu, Ming-Hui Weng, Jr-Hung Li, Yahru Cheng, Chi-Ming Yang, Tze-Liang Lee, Ching-Yu Chang
  • Patent number: 12191350
    Abstract: The present disclosure provides a method of manufacturing a semiconductor structure, and a semiconductor structure. The method of manufacturing a semiconductor structure includes: providing a base, where a channel is formed in the base; forming a gate conductive layer, where the gate conductive layer covers a part of the channel; and forming a semiconductor doped layer, where the semiconductor doped layer fills the channel and covers the gate conductive layer, and a doping concentration of the semiconductor doped layer at a side close to a top surface of the gate conductive layer is different from a doping concentration of the semiconductor doped layer at a side away from the top surface of the gate conductive layer.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: January 7, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Chih-Cheng Liu
  • Patent number: 12159836
    Abstract: A semiconductor structure and a method for fabricating a semiconductor structure are provided. In the semiconductor structure, a side of a film layer structure facing away from a substrate is provided with a wiring layer, a side of the substrate facing away from the film layer structure is provided with a connecting hole extending to the wiring layer, and an insulating layer is arranged on a hole wall of the connecting hole. A barrier ring is arranged on the insulating layer, a center line of the barrier ring is arranged collinearly with a center line of the connecting hole, and diffusibility of the barrier ring is less than diffusibility of the wiring layer. A connecting post joined to the wiring layer is arranged in the connecting hole.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: December 3, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Chih-Cheng Liu
  • Patent number: 12159828
    Abstract: Provided are a semiconductor structure and a method for manufacturing a semiconductor structure. The semiconductor structure includes: a through silicon via and a shielding structure disposed at an outer side of the through silicon via, in which the shielding structure includes at least two non-closed annular shielding layers surrounding the through silicon via and at least one conductive plug configured to connect two adjacent ones of the non-closed annular shielding layers; the at least two non-closed annular shielding layers and the at least one conductive plug are alternately distributed along an extending direction of the through silicon via and sequentially connected to form a conductive path, and current flow directions in two adjacent ones of the non-closed annular shielding layers in the conductive path are opposite.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: December 3, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Tzung-Han Lee, Chih-Cheng Liu
  • Patent number: 12159787
    Abstract: In a pattern formation method, a photoresist layer is formed over a substrate by combining a first precursor and a second precursor in a vapor state to form a photoresist material. The first precursor is an organometallic having a formula MaRbXc, where M is one or more selected from the group consisting of Sn, Bi, Sb, In, and Te, R is an alkyl group that is substituted by different EDG and/or EWG, X is a halide or sulfonate group, and 1?a?2, b?1, c?1, and b+c?4. The second precursor is water, an amine, a borane, and/or a phosphine. The photoresist material is deposited over the substrate, and selectively exposed to actinic radiation to form a latent pattern, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: December 3, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Cheng Liu, Ming-Hui Weng, Jr-Hung Li, Yahru Cheng, Chi-Ming Yang, Tze-Liang Lee, Ching-Yu Chang
  • Patent number: 12153346
    Abstract: An organometallic precursor for extreme ultraviolet (EUV) lithography is provided. An organometallic precursor includes a chemical formula of MaXbLc, where M is a metal, X is a multidentate aromatic ligand that includes a pyrrole-like nitrogen and a pyridine-like nitrogen, L is an extreme ultraviolet (EUV) cleavable ligand, a is between 1 and 2, b is equal to or greater than 1, and c is equal to or greater than 1.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: November 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Cheng Liu, Yi-Chen Kuo, Yen-Yu Chen, Jr-Hung Li, Chi-Ming Yang, Tze-Liang Lee
  • Publication number: 20240385514
    Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate, including combining a first precursor and a second precursor in a vapor state to form a photoresist material, and depositing the photoresist material over the substrate. A protective layer is formed over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation through the protective layer to form a latent pattern in the photoresist layer. The protective layer is removed, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hui WENG, Chen-Yu LIU, Chih-Cheng LIU, Yi-Chen KUO, Jia-Lin WEI, Yen-Yu CHEN, Jr-Hung LI, Yahru CHENG, Chi-Ming YANG, Tze-Liang LEE, Ching-Yu CHANG
  • Publication number: 20240385516
    Abstract: An organometallic precursor for extreme ultraviolet (EUV) lithography is provided. An organometallic precursor includes an aromatic di-dentate ligand, a transition metal coordinated to the aromatic di-dentate ligand, and an extreme ultraviolet (EUV) cleavable ligand coordinated to the transition metal. The aromatic di-dentate ligand includes a plurality of pyrazine molecules.
    Type: Application
    Filed: June 28, 2024
    Publication date: November 21, 2024
    Inventors: Chih-Cheng Liu, Yi-Chen Kuo, Yen-Yu Chen, Jr-Hung Li, Chi-Ming Yang, Tze-Liang Lee
  • Publication number: 20240387173
    Abstract: In a pattern formation method, a photoresist layer is formed over a substrate by combining a first precursor and a second precursor in a vapor state to form a photoresist material. The first precursor is an organometallic having a formula MaRbXc, where M is one or more selected from the group consisting of Sn, Bi, Sb, In, and Te, R is an alkyl group that is substituted by different EDG and/or EWG, X is a halide or sulfonate group, and 1?a?2, b?1, c?1, and b+c?4. The second precursor is water, an amine, a borane, and/or a phosphine. The photoresist material is deposited over the substrate, and selectively exposed to actinic radiation to form a latent pattern, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Cheng LIU, Ming-Hui WENG, Jr-Hung LI, Yahru CHENG, Chi-Ming YANG, Tze-Liang LEE, Ching-Yu CHANG
  • Publication number: 20240385523
    Abstract: Method of manufacturing semiconductor device includes forming photoresist layer over substrate. Forming photoresist layer includes combining first precursor and second precursor in vapor state to form photoresist material, wherein first precursor is organometallic having formula: MaRbXc, where M at least one of Sn, Bi, Sb, In, Te, Ti, Zr, Hf, V, Co, Mo, W, Al, Ga, Si, Ge, P, As, Y, La, Ce, Lu; R is substituted or unsubstituted alkyl, alkenyl, carboxylate group; X is halide or sulfonate group; and 1?a?2, b?1, c?1, and b+c?5. Second precursor is at least one of an amine, a borane, a phosphine. Forming photoresist layer includes depositing photoresist material over the substrate. The photoresist layer is selectively exposed to actinic radiation to form latent pattern, and the latent pattern is developed by applying developer to selectively exposed photoresist layer to form pattern.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Cheng LIU, Yi-Chen KUO, Jia-Lin WEI, Ming-Hui WENG, Yen-Yu CHEN, Jr-Hung LI, Yahru CHENG, Chi-Ming YANG, Tze-Liang LEE, Ching-Yu CHANG
  • Publication number: 20240377732
    Abstract: An organometallic precursor for extreme ultraviolet (EUV) lithography is provided. An organometallic precursor includes a chemical formula of MaXbLc, where M is a metal, X is a multidentate aromatic ligand that includes a pyrrole-like nitrogen and a pyridine-like nitrogen, L is an extreme ultraviolet (EUV) cleavable ligand, a is between 1 and 2, b is equal to or greater than 1, and c is equal to or greater than 1.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: Chih-Cheng Liu, Yi-Chen Kuo, Yen-Yu Chen, Jr-Hung Li, Chi-Ming Yang, Tze-Liang Lee
  • Patent number: 12135501
    Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate, including combining a first precursor and a second precursor in a vapor state to form a photoresist material, and depositing the photoresist material over the substrate. A protective layer is formed over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation through the protective layer to form a latent pattern in the photoresist layer. The protective layer is removed, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.
    Type: Grant
    Filed: August 3, 2023
    Date of Patent: November 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Hui Weng, Chen-Yu Liu, Chih-Cheng Liu, Yi-Chen Kuo, Jia-Lin Wei, Yen-Yu Chen, Jr-Hung Li, Yahru Cheng, Chi-Ming Yang, Tze-Liang Lee, Ching-Yu Chang