Patents by Inventor Chin Cheng Chien

Chin Cheng Chien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR DEVICE AND METHOD OF FORMING EPITAXIAL LAYER
    Publication number: 20130105861
    Abstract: A semiconductor device includes a semiconductor substrate and a plurality of transistors. The semiconductor substrate includes at least an iso region (namely an open region) and at least a dense region. The transistors are disposed in the iso region and the dense region respectively. Each transistor includes at least a source/drain region. The source/drain region includes a first epitaxial layer having a bottom thickness and a side thickness, and the bottom thickness is substantially larger than or equal to the side thickness.
    Type: Application
    Filed: November 1, 2011
    Publication date: May 2, 2013
    Inventors: Chin-I Liao, Teng-Chun Hsuan, Chin-Cheng Chien
  • Manufacturing method for semiconductor structure
    Patent number: 8426284
    Abstract: A manufacturing method for a semiconductor structure includes providing a substrate having at least a gate structure formed thereon, performing a first wet etching process to etch the substrate at two sides of the gate structure, performing a second wet etching process to etch the substrate to form a recess respectively at two sides of the gate structure, and performing a selective epitaxial growth method to form an epitaxial layer having a diamond shape with a flat bottom respectively in the recess.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: April 23, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chiu-Hsien Yeh, Chin-Cheng Chien, Yu-Wen Wang
  • Strained Silicon Channel Semiconductor Structure and Method of Making the Same
    Publication number: 20130092954
    Abstract: A method for fabricating a strained channel semiconductor structure includes providing a substrate, forming at least one gate structure on said substrate, performing an etching process to form two recesses in said substrate at opposites sides of said gate structure, the sidewall of said recess being concaved in the direction to said gate structure and forming an included angle with respect to horizontal plane, and performing a pre-bake process to modify the recess such that said included angle between the sidewall of said recess and the horizontal plane is increased.
    Type: Application
    Filed: October 17, 2011
    Publication date: April 18, 2013
    Inventors: Chan-Lon Yang, Ted Ming-Lang Guo, Chin-I Liao, Chin-Cheng Chien, Shu-Yen Chan, Chun-Yuan Wu
  • SEMICONDUCTOR PROCESS
    Publication number: 20130078780
    Abstract: A semiconductor process includes the following steps. An interlayer is formed on a substrate. A first metallic oxide layer is formed on the interlayer. A reduction process is performed to reduce the first metallic oxide layer into a metal layer. A high temperature process is performed to transform the metal layer to a second metallic oxide layer.
    Type: Application
    Filed: September 22, 2011
    Publication date: March 28, 2013
    Inventors: Chin-Fu Lin, Chih-Chien Liu, Teng-Chun Tsai, Chin-Cheng Chien, Chun-Yuan Wu
  • SEMICONDUCTOR PROCESS
    Publication number: 20130078778
    Abstract: A semiconductor process is described as follows. A plurality of dummy patterns is formed on a substrate. A mask material layer is conformally formed on the substrate, so as to cover the dummy patterns. The mask material layer has an etching rate different from that of the dummy patterns. A portion of the mask material layer is removed, so as to form a mask layer on respective sidewalls of each dummy pattern. An upper surface of the mask layer and an upper surface of each dummy pattern are substantially coplanar. The dummy patterns are removed. A portion of the substrate is removed using the mask layer as a mask, so as to form a plurality of fin structures and a plurality of trenches alternately arranged in the substrate. The mask layer is removed.
    Type: Application
    Filed: September 23, 2011
    Publication date: March 28, 2013
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Teng-Chun Tsai
  • Method of fabricating complementary metal-oxide-semiconductor (CMOS) device
    Patent number: 8404591
    Abstract: A method of fabricating a MOS device comprises steps as follows: An interfacial layer, a high-k dielectric layer and a cover layer on a substrate are sequentially formed. Then an in-situ wet etching step is performed by sequentially using a first etching solution to etch the cover layer and using a second etching solution to etch the high-k dielectric layer and the interfacial layer until the substrate is exposed, wherein the second etching solution is a mixed etching solution containing the first etching solution.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: March 26, 2013
    Assignees: United Microelectronics Corporation, Lam Research Corporation
    Inventors: Chiu-Hsien Yeh, Chan-Lon Yang, Chin-Cheng Chien, Lien-Fa Hung, Yun-Cheng Kao
  • Semiconductor structure with gate structure, source/drain region and recess filling with epitaxial layer
    Patent number: 8405155
    Abstract: A semiconductor structure comprises a substrate, a gate structure, at least a source/drain region, a recess and an epitaxial layer. The substrate includes an up surface. A gate structure is located on the upper surface. The source/drain region is located within the substrate beside the gate structure. The recess is located within the source/drain region. The epitaxial layer fills the recess, and the cross-sectional profile of the epitaxial layer is an octagon.
    Type: Grant
    Filed: September 23, 2010
    Date of Patent: March 26, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chiu-Hsien Yeh, Chun-Yuan Wu, Chin-Cheng Chien
  • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20130069172
    Abstract: A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes a gate structure, a source region and a drain region. The gate structure is disposed on a substrate. The source and drain regions disposed at respective sides of the gate structure include a boron-doped silicon germanium (SiGeB) layer substantially without stress relaxation. The boron-doped silicon germanium (SiGeB) layer has a germanium concentration greater than 30 at % and an in-situ doping concentration of boron ranging between 2.65×1020/cm3 and 1×1021/cm3.
    Type: Application
    Filed: September 16, 2011
    Publication date: March 21, 2013
    Applicant: United Microelectronics Corp.
    Inventors: CHIN-I LIAO, TENG-CHUN HSUAN, CHIN-CHENG CHIEN
  • NON-PLANAR SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
    Publication number: 20130056827
    Abstract: A non-planar semiconductor structure includes a substrate, at least two fin-shaped structures, at least an isolation structure, and a plurality of epitaxial layers. The fin-shaped structures are located on the substrate. The isolation structure is located between the fin-shaped structures, and the isolation structure has a nitrogen-containing layer. The epitaxial layers respectively cover a part of the fin-shaped structures and are located on the nitrogen-containing layer. A non-planar semiconductor process is also provided for forming the semiconductor structure.
    Type: Application
    Filed: September 2, 2011
    Publication date: March 7, 2013
    Inventors: Shih-Hung Tsai, Chien-Ting Lin, Chin-Cheng Chien, Chin-Fu Lin, Chih-Chien Liu, Teng-Chun Tsai, Chun-Yuan Wu
  • METHOD OF FORMING SEMICONDUCTOR DEVICE
    Publication number: 20130045579
    Abstract: A method of forming a semiconductor device includes the following steps. A semiconductor substrate having a first strained silicon layer is provided. Then, an insulating region such as a shallow trench isolation (STI) is formed, where a depth of the insulating region is substantially larger than a depth of the first strained silicon layer. Subsequently, the first strained silicon layer is removed, and a second strained silicon layer is formed to substitute the first strained silicon layer.
    Type: Application
    Filed: August 17, 2011
    Publication date: February 21, 2013
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Teng-Chun Tsai
  • SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME
    Publication number: 20130037886
    Abstract: A semiconductor device includes a semiconductor substrate, at least a first fin structure, at least a second fin structure, a first gate, a second gate, a first source/drain region and a second source/drain region. The semiconductor substrate has at least a first active region to dispose the first fin structure and at least a second active region to dispose the second fin structure. The first/second fin structure partially overlapped by the first/second gate has a first/second stress, and the first stress and the second stress are different from each other. The first/second source/drain region is disposed in the first/second fin structure at two sides of the first/second gate.
    Type: Application
    Filed: August 10, 2011
    Publication date: February 14, 2013
    Inventors: Teng-Chun Tsai, Chun-Yuan Wu, Chih-Chien Liu, Chin-Cheng Chien, Chin-Fu Lin
  • TEST PATTERN FOR MEASURING SEMICONDUCTOR ALLOYS USING X-RAY DIFFRACTION
    Publication number: 20130026464
    Abstract: A test pattern for measuring semiconductor alloys using X-ray diffraction (XRD) includes a first region to an Nth region defined on a wafer, and a plurality of test structures positioned in the first region and so forth up to in the Nth region. The test structures in the same region have sizes identical to each other and the test structures in different regions have sizes different from each other.
    Type: Application
    Filed: July 25, 2011
    Publication date: January 31, 2013
    Inventors: Chin-I Liao, Teng-Chun Hsuan, I-Ming Lai, Chin-Cheng Chien
  • SEMICONDUCTOR DEVICE HAVING EPITAXIAL STRUCTURES
    Publication number: 20130026538
    Abstract: A semiconductor device having epitaxial structures includes a gate structure positioned on a substrate, epitaxial structures formed in the substrate at two sides of the gate structure, and an undoped cap layer formed on the epitaxial structures. The epitaxial structures include a dopant, a first semiconductor material having a first lattice constant, and a second semiconductor material having a second lattice constant, and the second lattice constant is larger than the first lattice constant. The undoped cap layer also includes the first semiconductor material and the second semiconductor material. The second semiconductor material in the epitaxial structures includes a first concentration, the second semiconductor material in the undoped cap layer includes at least a first concentration, and the second concentration is lower than the first concentration.
    Type: Application
    Filed: July 25, 2011
    Publication date: January 31, 2013
    Inventors: Chin-I Liao, Teng-Chun Hsuan, I-Ming Lai, Chin-Cheng Chien
  • Fin field-effect transistor structure and manufacturing process thereof
    Patent number: 8361854
    Abstract: A fin field-effect transistor structure includes a substrate, a fin channel and a high-k metal gate. The high-k metal gate is formed on the substrate and the fin channel. A process of manufacturing the fin field-effect transistor structure includes the following steps. Firstly, a polysilicon pseudo gate structure is formed on the substrate and a surface of the fin channel. By using the polysilicon pseudo gate structure as a mask, a source/drain region is formed in the fin channel. After the polysilicon pseudo gate structure is removed, a high-k dielectric layer and a metal gate layer are successively formed. Afterwards, a planarization process is performed on the substrate having the metal gate layer until the first dielectric layer is exposed, so that a high-k metal gate is produced.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: January 29, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Teng-Chun Tsai, Chun-Yuan Wu, Chin-Fu Lin, Chih-Chien Liu, Chin-Cheng Chien
  • METAL OXIDE SEMICONDUCTOR TRANSISTOR AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20130020657
    Abstract: A method for manufacturing a MOS transistor is provided. A substrate has a high-k dielectric layer and a barrier in each of a first opening and a second opening formed by removing a dummy gate and located in a first transistor region and a second transistor region. A dielectric barrier layer is formed on the substrate and filled into the first opening and the second opening to cover the barrier layers. A portion of the dielectric barrier in the first transistor region is removed. A first work function metal layer is formed. The first work function metal layer and a portion of the dielectric barrier layer in the second transistor region are removed. A second work function metal layer is formed. The method can avoid a loss of the high-k dielectric layer to maintain the reliability of a gate structure, thereby improving the performance of the MOS transistor.
    Type: Application
    Filed: July 22, 2011
    Publication date: January 24, 2013
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Tsuo-Wen LU, Tzung-Ying Lee, Jei-Ming Chen, Chun-Wei Hsu, Yu-Min Lin, Chia-Lung Chang, Chin-Cheng Chien, Shu-Yen Chan
  • FABRICATING METHOD OF MOS TRANSISTOR, FIN FIELD-EFFECT TRANSISTOR AND FABRICATION METHOD THEREOF
    Publication number: 20130001707
    Abstract: A fabricating method of a MOS transistor includes the following steps. A substrate is provided. A gate dielectric layer is formed on the substrate. A nitridation process containing nitrogen plasma and helium gas is performed to nitride the gate dielectric layer. A fin field-effect transistor and fabrication method thereof are also provided.
    Type: Application
    Filed: June 30, 2011
    Publication date: January 3, 2013
    Inventors: Chien-Liang Lin, Ying-Wei Yen, Yu-Ren Wang, Chan-Lon Yang, Chin-Cheng Chien, Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Teng-Chun Tsai
  • METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
    Publication number: 20120326238
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region thereon; forming a high-k dielectric layer, a barrier layer, and a first metal layer on the substrate; removing the first metal layer of the second region; forming a polysilicon layer to cover the first metal layer of the first region and the barrier layer of the second region; patterning the polysilicon layer, the first metal layer, the barrier layer, and the high-k dielectric layer to form a first gate structure and a second gate structure in the first region and the second region; and forming a source/drain in the substrate adjacent to two sides of the first gate structure and the second gate structure.
    Type: Application
    Filed: June 24, 2011
    Publication date: December 27, 2012
    Inventors: Chin-Cheng Chien, Tzung-Ying Lee, Tsuo-Wen Lu, Shu-Yen Chan, Jei-Ming Chen, Yu-Min Lin, Chun-Wei Hsu
  • MANUFACTURING METHOD FOR METAL GATE
    Publication number: 20120329261
    Abstract: A manufacturing method for a metal gate includes providing a substrate having at least a semiconductor device with a conductivity type formed thereon, forming a gate trench in the semiconductor device, forming a work function metal layer having the conductivity type and an intrinsic work function corresponding to the conductivity type in the gate trench, and performing an ion implantation to adjust the intrinsic work function of the work function metal layer to a target work function.
    Type: Application
    Filed: June 21, 2011
    Publication date: December 27, 2012
    Inventors: Shao-Wei Wang, Yu-Ren Wang, Chien-Liang Lin, Wen-Yi Teng, Tsuo-Wen Lu, Chih-Chung Chen, Ying-Wei Yen, Yu-Min Lin, Chin-Cheng Chien, Jei-Ming Chen, Chun-Wei Hsu, Chia-Lung Chang, Yi-Ching Wu, Shu-Yen Chan
  • THROUGH-SILICON VIA FORMING METHOD
    Publication number: 20120322260
    Abstract: A through-silicon via forming method includes the following steps. Firstly, a semiconductor substrate is provided. Then, a through-silicon via conductor is formed in the semiconductor substrate, and a topside of the through-silicon via conductor is allowed to be at the same level as a surface of the semiconductor substrate. Afterwards, a portion of the through-silicon via conductor is removed, and the topside of the through-silicon via conductor is allowed to be at a level lower than the surface of the semiconductor substrate, so that a recess is formed over the through-silicon via conductor.
    Type: Application
    Filed: June 16, 2011
    Publication date: December 20, 2012
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Teng-Chun Tsai, Chun-Yuan Wu, Chin-Fu Lin, Chih-Chien Liu, Chin-Cheng Chien
  • SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF
    Publication number: 20120319198
    Abstract: A semiconductor device including a substrate, a spacer and a high-k dielectric layer having a U-shape profile is provided. The spacer located on the substrate surrounds and defines a trench. The high-k dielectric layer having a U-shape profile is located in the trench, and the high-k dielectric layer having a U-shape profile exposes an upper portion of the sidewalls of the trench.
    Type: Application
    Filed: June 16, 2011
    Publication date: December 20, 2012
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Teng-Chun Tsai