Abstract: An electronic device includes a substrate, a plurality of flexible circuit boards, a plurality of ICs and an insulator. The flexible circuit boards are disposed on the substrate. In a top view of the electronic device, the flexible circuit boards are overlapped with an edge of the substrate. The ICs are disposed on the substrate. The insulator is disposed on the flexible circuit boards and contacted the ICs, wherein the insulator has a first side and a second side opposite to the first side and the first side is closer to the edge than the second side. Along a first direction perpendicular to an extension direction of the edge, a first minimum distance between the second side and one of the ICs is less than a second minimum distance between the second side and one of the flexible circuit boards.

Abstract: A semiconductor structure including a substrate and a pad structure is provided. The pad structure is located on the substrate. The pad structure includes material pairs and pads. The material pairs are stacked on the substrate to form a stair step structure. Each of the material pairs includes a conductive layer and a dielectric layer located on the conductive layer. Each of the pads includes a conductive pillar and a pad layer. The conductive pillar is embedded in the material pair and is connected to the conductive layer of the material pair. The pad layer is located on the conductive pillar.

Abstract: A method of fabricating a memory device includes patterning a stacked structure to form a first staircase structure and a second staircase structure; patterning a conductive layer under the stacked structure to form a first slit trench along a first direction; forming a first dielectric layer overlaying the first staircase structure and the second staircase structure and filling into the first slit trench, wherein the first dielectric layer filled in the first slit trench forms a first slit; patterning the first dielectric layer, the stacked structure, and the conductive layer to form multiple second slit trenches, wherein the second slit trenches along a second direction perpendicular to the first direction; performing a replacement process to replace the sacrificial layers with multiple gate conductive layers; and filling a second dielectric layer in the second slit trenches to form multiple second slits.

Abstract: The present invention utilizes a high-speed intensive mixer in a fluidizing-type, solid-phase, neutralization reactor to blend solid-state alkali hydroxide with any humic acid sources. The final product is a dry humic acid salt. The purpose of this innovative method is to eliminate a series of complicated unit operations commonly employed by the traditional process. These removed steps may include dissolving caustic soda, mixing in a paste-like formation, extrusion, granulation, drying, and grinding, etc. The invention contributes to a simplified flowsheet, resulting in sharply reduced equipment investment, plant space, and labor and energy costs. All of these factors coupled with increased productivity will drastically lower the overall production cost. Also, the reduction of dust pollution will greatly minimize the impact in environmental protection and safety issues.

Abstract: A memory device includes a dielectric substrate, an interlayer structure, a plurality of channel pillars, a plurality of charge storage structures, a plurality of slit structures and an assistance structure. The dielectric substrate includes an array region and an iso region aside the array region. The interlayer structure is disposed in the array region and the iso region. The channel pillars penetrate through the interlayer structure in the array region. The charge storage structures are disposed between the interlayer structure and the plurality of channel pillars. The slit structures are disposed between the plurality of channel pillars, penetrate through the interlayer structure in the array region, and divide the interlayer structure into a plurality of blocks. The assistance structure is arranged in the iso region. The assistance structure includes at least one dummy slit structure having an extension direction different from an extension direction of the plurality of slit structures.

Abstract: A routing pattern is provided. The routing pattern includes a first routing region, a second routing region and an interconnection region. The first routing region includes a plurality of first conductive lines extending along a first direction. The plurality of first conductive lines has a first pitch along a second direction perpendicular to the first direction. The second routing region includes a plurality of second conductive lines extending along the first direction. The plurality of second conductive lines has a second pitch along the second direction, and the second pitch is approximately equal to the first pitch. The interconnection region includes two body parts and a connecting part connecting to the body parts. The body parts are disposed separately along the first direction. A width of the connecting part along the second direction is smaller than a width of the body parts along the second direction.

Abstract: A memory device includes a substrate, a metal interconnect structure, a first stack structure, a second stack structure, a first conductive pillar, and a first contact. The metal interconnect structure is located on the substrate. The first stack structure is located on the metal interconnect structure and includes first conductive layers and first insulating layer that alternate with each other, and an insulating structure embedded in the first conductive layers and the first insulating layers. The second stack structure is located on the first stack structure and includes second insulating layers and middle layers that alternate with each other. The first conductive pillar is embedded in the insulating structure to be electrically connected to the metal interconnect structure. The first contact passes through the second insulating layers and the middle layers of the second stack structure to be electrically connected to the first conductive pillar.

Abstract: A method of fabricating a memory device includes patterning a stacked structure to form a first staircase structure and a second staircase structure; patterning a conductive layer under the stacked structure to form a first slit trench along a first direction; forming a first dielectric layer overlaying the first staircase structure and the second staircase structure and filling into the first slit trench, wherein the first dielectric layer filled in the first slit trench forms a first slit; patterning the first dielectric layer, the stacked structure, and the conductive layer to form multiple second slit trenches, wherein the second slit trenches along a second direction perpendicular to the first direction; performing a replacement process to replace the sacrificial layers with multiple gate conductive layers; and filling a second dielectric layer in the second slit trenches to form multiple second slits.

Abstract: A memory device includes a staircase structure, multiple first plugs, multiple second plugs, and multiple third plugs. The staircase structure includes multiple gate layers and multiple insulating layers alternately stacked on each other, and the staircase structure includes multiple first blocks and multiple second blocks which alternate with each other. The first plugs are disposed in the first blocks, and the first plugs in a same first block are staggered with each other. The second plugs are disposed in the first blocks. The second plugs in a same first block are staggered with each other, and the first plugs and the second plugs in a same first block are staggered with each other. The third plugs are disposed in the second blocks.

Abstract: The present invention utilizes a high-speed intensive mixer in a fluidizing-type, solid-phase, neutralization reactor to blend solid-state alkali hydroxide with any humic acid sources. The final product is a dry humic acid salt. The purpose of this innovative method is to eliminate a series of complicated unit operations commonly employed by the traditional process. These removed steps may include dissolving caustic soda, mixing in a paste-like formation, extrusion, granulation, drying, and grinding, etc. The invention contributes to a simplified flowsheet, resulting in sharply reduced equipment investment, plant space, and labor and energy costs. All of these factors coupled with increased productivity will drastically lower the overall production cost. Also, the reduction of dust pollution will greatly minimize the impact in environmental protection and safety issues.

Abstract: The present invention utilizes a high-speed intensive mixer in a fluidizing-type, solid-phase, neutralization reactor to blend solid-state alkali hydroxide with any humic acid sources. The final product is a dry humic acid salt. The purpose of this innovative method is to eliminate a series of complicated unit operations commonly employed by the traditional process. These removed steps may include dissolving caustic soda, mixing in a paste-like formation, extrusion, granulation, drying, and grinding, etc. The invention contributes to a simplified flowsheet, resulting in sharply reduced equipment investment, plant space, and labor and energy costs. All of these factors coupled with increased productivity will drastically lower the overall production cost. Also, the reduction of dust pollution will greatly minimize the impact in environmental protection and safety issues.

Abstract: Reference marks for forming a staircase structure are disposed along slit areas of a 3D memory structure, and slits of the 3D memory structure are formed on the slit areas. In a staircase area, the reference marks are formed by etching the topmost one of stacked layers, having a pair of a dielectric layer and a sacrificial layer, in a stacked structure.

Abstract: Reference marks for forming a staircase structure are disposed along slit areas of a 3D memory structure, and slits of the 3D memory structure are formed on the slit areas. In a staircase area, the reference marks are formed by etching the topmost one of stacked layers, having a pair of a dielectric layer and a sacrificial layer, in a stacked structure.

Abstract: The present invention utilizes a high-speed intensive mixer in fluidizing type solid phase neutralization reactor to blend solid state alkali hydroxide with any humic acid sources. The final product is a dry humic acid salt. The purpose of this innovative method is to eliminate a series of complicated unit operations commonly employed by the traditional process. These removed steps may include dissolving caustic soda, mixing in a paste like formation, extrusion, granulation, drying, and grinding, etc. The new invention contributes to a simplified flowsheet, resulting in sharply reduced equipment investment, the required plant space, and labor and energy costs. All these factors coupled with increased productivity will drastically lower the overall production cost. Also the reduction of dust pollution will greatly minimize the impact in environmental protection and safety issues.

Abstract: A semiconductor device and method of fabricating the same are provided. The semiconductor device includes a substrate having a trench and an etching stop layer. The etching stop layer is disposed in the substrate and surrounds the bottom surface and a portion of a sidewall of the trench.

Abstract: A circuit structure comprises a plurality of first conducting lines extending in a first direction, the first conducting lines having a first pitch in a second direction orthogonal to the first direction; a plurality of linking lines extending in the second direction, the linking lines having a second pitch in the first direction, the second pitch being greater than the first pitch; and a plurality of connection structures connecting respective first conducting lines for current flow to respective linking lines, the connection structures each including a plurality of segments extending in the first direction, segments in the plurality of segments having a transition pitch in the second direction relative to adjacent segments in the plurality of segments greater than or equal to the first pitch, and less than the second pitch.

Abstract: A circuit structure comprises a plurality of first conducting lines extending in a first direction, the first conducting lines having a first pitch in a second direction orthogonal to the first direction; a plurality of linking lines extending in the second direction, the linking lines having a second pitch in the first direction, the second pitch being greater than the first pitch; and a plurality of connection structures connecting respective first conducting lines for current flow to respective linking lines, the connection structures each including a plurality of segments extending in the first direction, segments in the plurality of segments having a transition pitch in the second direction relative to adjacent segments in the plurality of segments greater than or equal to the first pitch, and less than the second pitch.

Abstract: A method for forming an aligned mask comprises etching a reference mark on a substrate to demarcate a boundary of an etch region; forming an etch mask on the substrate, using an exposure setting, the etch mask having a boundary; and measuring a distance between the reference mark and the boundary. When the measured distance is outside a margin of a target distance, then the etch mask is removed from the substrate, the exposure setting is changed, a next etch mask is formed using the changed exposure setting, and said measuring is repeated. A set of reference marks can be etched on a top level in a set of levels to demarcate boundaries of etch regions. An etch-trim process can be performed to form steps in the set of levels, wherein the etch-trim process includes at least first and second etch-trim cycles using first and second reference marks.

Abstract: Multilevel circuitry such as a a 3D memory array, has a set of contact regions arranged around a perimeter of a multilevel region, in which connection is made to circuit elements in a number W levels. Each of the contact regions has a number of steps having landing areas thereon, including steps on up to a number M levels, where the number M can be much less than W. A combination of contact regions provides landing areas on all of the W levels, each of the contact regions in the combination having landing areas on different subsets of the W levels. A method of forming the device uses an etch-trim process to form M levels in all of the contact regions, and one or more anisotropic etches in some of the contact regions.

Abstract: A method for forming an aligned mask comprises etching a reference mark on a substrate to demarcate a boundary of an etch region; forming an etch mask on the substrate, using an exposure setting, the etch mask having a boundary; and measuring a distance between the reference mark and the boundary. When the measured distance is outside a margin of a target distance, then the etch mask is removed from the substrate, the exposure setting is changed, a next etch mask is formed using the changed exposure setting, and said measuring is repeated. A set of reference marks can be etched on a top level in a set of levels to demarcate boundaries of etch regions. An etch-trim process can be performed to form steps in the set of levels, wherein the etch-trim process includes at least first and second etch-trim cycles using first and second reference marks.