Abstract: An overlay mark is used in pattern registration on a semiconductor wafer with an oxide layer. Four sets of two trenches each are formed in the oxide layer. Each trench in a set is parallel to the other trench of the same set. The trenches are configured such that each set forms one side of a box shape.

Abstract: The present invention provides a semiconductor device with a metal-to-contact overlay structure. The semiconductor device includes a substrate, a dielectric layer on the substrate, a contact coupled to the substrate in the dielectric layer, a first conductive region on the contact in the dielectric layer, a dielectric sidewall on the contact in the dielectric layer, the dielectric sidewall surrounding the first conductive region, and a second conductive region on the first conductive region on the dielectric layer.

Abstract: A method of manufacturing a memory device is disclosed. The method includes providing a substrate, forming a number of memory sectors on the substrate, wherein each of the memory sectors is coupled to an adjacent one via a first diffused region in the substrate and is coupled to another adjacent one via at least one second diffused region in the substrate, forming a first dielectric layer on the memory sectors, forming a first conductive structure through the first dielectric layer to the first diffused region, and at least one second conductive structure through the first dielectric layer to the at least one second diffused region, forming a patterned first mask layer on the first dielectric layer, the first conductive structure and the at least one second conductive structure, the patterned first mask layer exposing the first conductive structure, and etching back the first conductive structure.

Abstract: A semiconductor memory device includes a substrate, a patterned dielectric layer on the substrate, a patterned conductive layer on the patterned dielectric layer, and a plurality of isolation structures to provide electrical isolation for the patterned conductive layer. Each of the isolation structures includes a base in the substrate, a first bank extending from the base to the patterned conductive layer, and a second bank extending from the base to the patterned conductive layer, the first bank and the second bank being separated from each other over the substrate.

Abstract: An overlay mark arrangement for reducing the asymmetric profile and an overlay shift during an integrated circuit manufacturing process is disclosed. In one embodiment, the overlay mark arrangement may comprise a first mark, a second mark and a stress releasing means. The first mark is used to indicate the position of a lower layer, the second mark is used to indicate the position of an upper layer; and the stress releasing means is used to release the film stress induced by the upper layer. Unlike the conventional overlay mark arrangements, which will have a severe overlay mark shift due to the film stress, the asymmetric overlay mark profile can be improved by using multiple trenches around the overlay marks according to certain embodiments of the invention disclosed herein.

Abstract: A mask for producing an image feature on an image surface during a semiconductor fabrication process is provided, the mask comprising a main feature having opaque areas and transmissive areas arranged in the form of the image feature, wherein each end of the main feature includes at least one of an opaque edge and a transmissive edge, wherein the opaque edge includes a set of transmissive assist features arranged therein such that the set of transmissive assist features align alternately with the transmissive areas of the main feature, and the transmissive edge includes a set of opaque assist features arranged therein such that the set of opaque assist features align alternately with the opaque areas of the main feature.

Abstract: A wafer structure includes a plurality of dies, an edge portion, a passivation layer, and a UV-blocking metal layer. Each of the dies having an integrated circuit formed thereon, and the circuit includes an upmost metal layer that includes bonding pads. A composite dielectric layer corresponding to dielectric layers of the integrated circuit is disposed on the edge portion, and a cavity is formed in the composite dielectric layer over the edge portion. The passivation layer is located over the whole wafer and covers the upmost metal layer. The UV-blocking metal layer is located on the passivation layer and covers the edge portion and at least a portion of each of the dies. The cavity, the passivation layer, and the UV-blocking metal layer result in an alignment mark.

Abstract: A method for registering a pattern on a semiconductor wafer with an oxide surface includes etching into the surface four sets of two trenches each. Each trench in a set is parallel to the other. The trenches are configured such that each set forms one side of a box shape. The trenches are overfilled with a first metal layer, the excess of which is removed so that the height of the metal is level with the height of the oxide. An overlay setting is then obtained between a photoresist mask and the filled trenches before depositing a second metal layer over the oxide and trenches. The second metal layer is coated with the photoresist according to the overlay setting.

Abstract: A photomask structure is described, including a substrate having multiple half-tone phase shift patterns on a device region and multiple opaque patterns on a die seal ring region. By using the photomask, a side lobe effect does not occur to the photoresist layer corresponding to the die seal ring region in the exposure step.

Abstract: An exposure process is described, for defining in a photoresist layer a plurality of first patterns having a first pitch and a second pattern between them that is wider than one first pattern. A first exposure step is conducted to the photoresist layer with a first photomask that has a plurality of the first patterns without a second pattern between them, wherein the first patterns on the first photomask have the first pitch only. A second exposure step is conducted to the photoresist layer with a second photomask that has a third pattern narrower than the second pattern at a position corresponding to the second pattern. The exposure dose of the first or second exposure step alone is not sufficient to define any pattern in the photoresist layer.

Abstract: A method of enabling alignment of a wafer in at least one exposure step of an integrated circuit process after a UV-blocking metal layer is formed over the whole wafer covering a patterned upmost metal layer of the integrated circuit is described, wherein the wafer has an edge portion where a composite dielectric layer corresponding to the dielectric layers of the integrated circuit is formed. The method includes forming a cavity in the composite dielectric layer over the edge portion of the wafer in the patterning process of the upmost metal layer, such that an alignment mark is formed after the UV-blocking metal layer is formed.

Abstract: The invention is directed to a method for patterning a material layer. The method comprises steps of forming a mask layer on the material layer. A multiple patterning process is performed on the mask layer for transferring at least a first pattern from a first photomask through a first photoresist and a second pattern from a second photomask from a second photoresist layer into the mask layer without performing any etching process. The mask layer exposes a portion of the material layer and the mask layer is patterned at the time that the first photoresist layer and the second photoresist layer are developed respectively. An etching process is performed to pattern the material layer by using the mask layer as an etching mask.

Abstract: A method and an apparatus for transferring a substrate are described. In the method, a substrate is provided on the surface of a first plate at a first position, the first plate is moved from the first position to a second position in an upper space of a second plate, the substrate is lifted away from the surface of the first plate, the first plate is moved away from the second position, and the substrate is put on the surface of the second plate from the upper space. The apparatus includes a first plate and a second plate each having a surface for carrying the substrate, wherein the first plate can be moved between the first position and the second position.

Abstract: An overlay mark is described, wherein the overlay mark is used for checking the alignment accuracy between a lower layer defined by two exposure steps and a lithography process for defining an upper layer, including a part of the lower layer and a photoresist patter. The part of the lower layer includes two first x-directional, two first y-directional bar-like patterns. The first x-directional and first y-directional bar-like patterns are defined by one exposure step to define a first rectangle. The second x-directional and second y-directional bar-like patterns are defined by another exposure to define a second rectangle, wherein the second rectangle is wider than the first rectangle. The photoresist pattern, which is formed by the lithograph process, is disposed over the part of the lower layer and is surrounded by the bar-like patterns.

Abstract: A method of patterning a target layer on a substrate is described. A patterned photoresist layer is formed over the target layer, wherein the patterned photoresist layer has unexposed parts as separate islands and each unexposed part has a low proton concentration at least in its sidewalls. Acid-crosslinked polymer layers are formed only on the sidewalls of each unexposed part. A flood exposure step is performed to the substrate. A baking step is performed to the patterned photoresist layer. A development step is performed to remove the previously unexposed parts. The target layer is etched with the acid-crosslinked polymer layers as a mask.

Abstract: The invention is directed to a method for patterning a material layer. The method comprises steps of providing a material layer. The material layer has a first hard mask layer and a second hard mask layer successively formed thereon. Then, the second hard mask layer is patterned to form a plurality of openings therein. A patterned photoresist layer is formed to cover the second hard mask layer and the patterned photoresist layer exposes a portion of the openings. The first hard mask layer with the patterned photoresist layer and the patterned second hard mask layer together as a mask. Then, the patterned photoresist layer and the patterned second hard mask layer are removed. The material layer is patterned with the patterned first hard mask layer as a mask.

Abstract: The invention is directed to a mark pattern for forming a process monitor mark in a patterned underlayer to monitor a patterning result of a photoresist layer over the patterned underlayer around the boundary between a peripheral region and a device region of a die, wherein the patterned underlayer is formed by using a first mask having a first pattern in a main region of the first mask and the mark pattern at an unused region of the first mask and the first pattern possesses a first mask critical dimension. The mark pattern comprising: a second pattern and a frame pattern. The second pattern has a second mask critical dimension, wherein the second mask critical dimension is as same as the first mask critical dimension. The frame pattern encloses the second pattern.

Abstract: The invention is directed to a method for determining an overlay correlation set between two successive patterned material layers on a substrate. The method comprises steps of providing a first material layer having a first overlay mark formed therein over the substrate and then using an exposure tool with a first overlay correlation set to form a patterned photoresist layer on the first material layer, wherein the patterned photoresist layer comprises a mark pattern and the mark pattern is located over the first overlay mark for defining a later formed second material layer on the first material layer to be a second overlay mark. Thereafter, a pre-process metrology overlay parameter set between the first overlay mark and the mark pattern is obtained. The first overlay correlation set at the exposure tool is adjusted according to the pre-process metrology overlay parameter set.

Abstract: An overlay mark is described, including N sets of parallel x-directional linear patterns respectively defined by N (?2) exposure steps and N sets of parallel y-directional linear patterns respectively defined by the N exposure steps, and a set of parallel x-directional photoresist bars and a set of parallel y-directional photoresist bars both formed in a lithography process. The N sets of x-directional linear patterns and the set of x-directional photoresist bars are arranged in parallel. The N sets of y-directional linear patterns and the set of y-directional photoresist bars are arranged in parallel.

Abstract: A baking apparatus including a hot plate and a substrate rotation member is provided. The hot plate has a heating surface. The substrate rotation member includes a rotation ring and a plurality of support arms. The rotation ring is configured to surround the hot plate. The support arms are disposed over the heating surface of the hot plate. Each of the support arms includes a connection part and a support part, wherein the connection part is configured to connect the rotation ring and the support part, and a supporting surface of the support part for supporting the substrate is higher than the heating surface of the hot plate.