Abstract: Provided is a semiconductor device including a substrate and a stack layer. The substrate includes a first region, a second region, and a third region. The third region is disposed between the first region and the second region. Since a top surface of the substrate in the first region is lower than the top surface of the substrate in the second region, the substrate in the third region has a first step height. The stack layer is disposed on the substrate in the first and third regions. The top surface of the stack layer in the first region and the third region and the top surface of the substrate in the second region are substantially coplanar.

Abstract: A lay-out arrangement for LC modules in 3D semiconductor memories is described that avoids large step height. The arrangement creates insulating/conducting layer pairs with adjacent pairs differing in height by no more than the thickness of two insulating/conducting layer pairs.

Abstract: A patterning method is provided. A substrate including a material layer thereon is provided. A patterned hard mask layer, having a plurality of first holes, is formed on the material layer. Afterward, a mask layer, including a plurality of line pattern masks extending in a direction and dividing each first hole into a second hole and a third hole, is formed. The material layer is patterned using the patterned hard mask layer and the mask layer as masks to form a patterned material layer having a plurality of fourth and fifth holes. Furthermore, a semiconductor structure is provided.

Abstract: Provided is a semiconductor device including a substrate and a stack layer. The substrate includes a first region, a second region, and a third region. The third region is disposed between the first region and the second region. Since a top surface of the substrate in the first region is lower than the top surface of the substrate in the second region, the substrate in the third region has a first step height. The stack layer is disposed on the substrate in the first and third regions. The top surface of the stack layer in the first region and the third region and the top surface of the substrate in the second region are substantially coplanar.

Abstract: A method of monitoring mask uniformity includes selecting a unit monitor mark pattern and monitor mark locations based on a main cell size, determining a unit monitor mark sampling location and measurement methodology, and starting a mask making process. The mask critical dimension uniformity (CDU) is measured and data is analyzed. A process impact factor is identified if the mask CDU is not within a predetermined specification, and a mask making process parameter is adjusted based on the identified process impact factor. The mask making process, measuring, identifying and adjusting steps are repeated until the mask CDU is within the predetermined specification.

Abstract: A method of forming a semiconductor device is disclosed. A substrate having a first area and a second area is provided. A target layer and a hard mask layer are sequentially formed on the substrate in the first area and in the second area. Transfer patterns are formed in a spacer form on the hard mask layer in the first area. A photoresist layer is formed directly on the hard mask layer, and covers the transfer patterns and the hard mask layer in the first area and in the second area. The photoresist layer in the first area is removed. The hard mask layer is patterned by using the transfer patterns as a mask.

Abstract: A three-dimensional stacked IC device includes a stack of at least first, second, third and fourth contact levels at an interconnect region. Each contact level has a conductive layer and an insulation layer. First, second, third and fourth electrical conductors pass through portions of the stack of contact levels. The first, second, third and fourth electrical conductors are in electrical contact with the first, second, third and fourth conductive layers, respectively. A dielectric sidewall spacer circumferentially surrounds the second, third and fourth electrical conductors so that the second, third and fourth electrical conductors only electrically contact the respective second, third and fourth conductive layers.

Abstract: A scanner and a method for performing an exposure process through a photomask on a wafer are provided. The exposure process includes an alignment step and an exposure step. The method includes the steps of moving a wafer table to align the wafer with an alignment apparatus, wherein the wafer table includes at least one chuck hole to attach the wafer to the wafer table by vacuum chucking, detecting an actual position of each of a plurality of alignment marks on the wafer, calculating an index value based on a difference between a predicted position and the actual position of each alignment mark, adjusting a vacuum pressure of the at least one chuck hole in the alignment step when the index value is larger than a first threshold value, and finishing the exposure process when the index value is smaller than or equal to the first threshold value.

Abstract: A wafer-level coating method and a coating system are provided. A strip-shaped sprayer is disposed above the wafer, and a length of the strip-shaped sprayer is larger than a diameter of the wafer. Then, a coating process is performed by spraying a material from the strip-shaped sprayer to form a material layer covering a top surface of the wafer and moving the strip-shaped sprayer relative to the wafer in a direction vertical to a length direction of the strip-shaped sprayer for at least a distance equal to or larger than the diameter of the wafer. Next, the moving strip-shaped sprayer and the spraying of the material are stopped after the material layer is formed.

Abstract: The invention is directed to an alignment mark in a material layer in an alignment region of a wafer. The alignment mark comprises a plurality of sub-marks. Each of the sub-mark comprises a first element and a plurality of second elements. The second elements are embedded in the first element and a first top surface of the first element is at the same height as a second top surface of each of the second elements.

Abstract: A method for forming separate narrow lines is described. A target layer is formed over a substrate. Base patterns are formed over the target layer. Target line patterns and connection patterns between the ends of the target line patterns are formed as spacers on the sidewalls of the base patterns. The base patterns are removed. The target line patterns and the connection patterns are transferred to the target layer to form target lines and connection segments between the ends of the target lines. At least a portion of each connection segment is removed to disconnect the target lines while other area of the substrate is subjected to a patterned removal treatment.

Abstract: A method of manufacturing using a double patterning method is provided. The double patterning method uses a first developer and a second developer that are different. For example, the first developer may be a positive tone developer for a positive photoresist while the second developer may be a negative tone developer for the positive photoresist. Photoresists having a photoactive compound are also provided that may be useful in double patterning methods. The resulting double patterning results, wherein a dimension of a variable first dense pattern is larger than a dimension of a variable second dense pattern.

Abstract: An apparatus, system, or method for positioning a wafer on a support of a rotatable chuck may improve the accuracy and precision of various wafer edge cuts and wafer profiling at a variety of stages of wafer manufacturing. The apparatus, system, or and/or method may employ one or more of a wafer position calculator to calculate a desired wafer position and to provide desired wafer position information to a wafer arm controller; and a wafer arm controller in communication with the wafer position calculator to provide instructions to adjust a wafer arm to position the wafer on the support according to the desired wafer position. Various sensor detectors and sensor lights or other mechanisms for sensing the position of a wafer may also be used.

Abstract: A method for forming separate narrow lines is described. A target layer is formed over a substrate. Base patterns are formed over the target layer. Target line patterns and connection patterns between the ends of the target line patterns are formed as spacers on the sidewalls of the base patterns. The base patterns are removed. The target line patterns and the connection patterns are transferred to the target layer to form target lines and connection segments between the ends of the target lines. At least a portion of each connection segment is removed to disconnect the target lines while other area of the substrate is subjected to a patterned removal treatment.

Abstract: A method for patterning a multi-layer film in a semiconductor device is provided. The semiconductor device comprises a substrate and a multi-layer film on the substrate. The multi-layer film comprises N conductive layers and N dielectric layers alternatingly stacked, and 2N contact plugs. The Nth dielectric layer is formed at the top of the multi-layer film. The distances between the centers of each adjacent contact plugs are the same.

Abstract: A method of manufacturing using a double patterning method is provided. The double patterning method uses a first developer and a second developer that are different. For example, the first developer may be a positive tone developer for a positive photoresist while the second developer may be a negative tone developer for the positive photoresist. Photoresists having a photoactive compound are also provided that may be useful in double patterning methods. The resulting double patterning results, wherein a dimension of a variable first dense pattern is larger than a dimension of a variable second dense pattern.

Abstract: A method and an apparatus for transferring a substrate are described. In the method, a substrate is provided on the surface of a first plate at a first position, the first plate is moved from the first position to a second position in an upper space of a second plate, the substrate is lifted away from the surface of the first plate, the first plate is moved away from the second position, and the substrate is put on the surface of the second plate from the upper space. The apparatus includes a first plate and a second plate each having a surface for carrying the substrate, wherein the first plate can be moved between the first position and the second position.

Abstract: A photo resist layer includes a first region and a second region. A treatment layer is applied to the photo resist layer.

Abstract: A method of manufacturing using a double patterning method is provided. The double patterning method uses a first developer and a second developer that are different. For example, the first developer may be a positive tone developer for a positive photoresist while the second developer may be a negative tone developer for the positive photoresist. Photoresists having a photoactive compound are also provided that may be useful in double patterning methods.

Abstract: An apparatus for wafer edge exposure comprises a first exposure unit and a second exposure unit. The first exposure unit includes a first light source to emit first light of multiple wavelengths, and a first mask to direct the first light toward a first area at an edge portion of a wafer. The second exposure unit includes a second light source to emit second light of a single wavelength, and a second mask to direct the second light toward a second area at the edge portion of the wafer. The second area encloses a transition area that borders the first area under the first mask.