Abstract: A manufacturing method of a semiconductor wafer includes forming a plurality of alignment trenches in the wafer substrate. A dielectric layer is formed over the substrate filling the trenches. A planarization process is performed to remove the dielectric layer above the substrate. A photolithograph process is subsequently performed to selectively remove the dielectric layer formed in the trenches in the alignment area.

Abstract: A method for registering a pattern on a semiconductor wafer with an oxide surface includes etching into the surface four sets of two trenches each. Each trench in a set is parallel to the other. The trenches are configured such that each set forms one side of a box shape. The trenches are overfilled with a first metal layer, the excess of which is removed so that the height of the metal is level with the height of the oxide. An overlay setting is then obtained between a photoresist mask and the filled trenches before depositing a second metal layer over the oxide and trenches. The second metal layer is coated with the photoresist according to the overlay setting.

Abstract: An overlay mark for checking the alignment accuracy between a lower layer and a lithography process for defining an upper layer is described, including a part of the lower layer having two first x-directional trenches, two first y-directional trenches, two second x-directional trenches and two second y-directional trenches therein, and two x-directional and two y-directional photoresist bars thereover that are surrounded by the trenches and formed in the lithography process. When the lower layer is fully aligned with the lithography process, the intersection of the central line of the two first x-directional trenches and that of the two first y-directional trenches, the intersection of the central line of the two second x-directional trenches and that of the two second y-directional trenches and the intersection of the central line of the two x-directional photoresist lines and that of the two y-directional photoresist lines coincide with each other.

Abstract: A method of fabricating a shallow trench isolation structure is provided. A substrate is provided with a pad layer, a mask layer and a shallow trench formed therein. A liner oxide layer is formed on the sidewall of the shallow trench and then a silicon nitride layer is formed conformably over the substrate. A developable material layer is formed to fill up the shallow trench. After the baking process, a part of the developable material layer is removed until the top surface of the developable material layer is lower than that of the substrate. The silicon nitride layer that is exposed by the developable material layer is removed and the remained developable material layer is removed. Following a thermal oxidation process, an insulating layer is formed over the substrate and fills up the shallow trench. After planarization and removing the mask layer, a shallow trench isolation structure is formed.

Abstract: A photomask with alignment marks for the current layer is provided with four edges. The photomask includes main patterns, an inter-scribe lane pattern sited between the main patterns, an extra-scribe lane pattern only sited on the three edges of the photomask, a first set of alignment marks for the current layer on opposite edges having the extra-scribe lane patterns. The photomask further includes a second set of alignment marks for the current layer on opposite edges in which only one has the extra-scribe lane pattern, and they are placed on opposite locations in the inter-scribe lane pattern and the extra-scribe lane pattern, respectively. Moreover, each one of the second set of alignment marks for the current layer include multiple parallel patterns and at least one vertical pattern sited on at least one end of the parallel patterns which are parallel to an extended direction of the opposite edges.

Abstract: A method of fabricating a shallow trench isolation structure is provided. A substrate is provided with a pad layer, a mask layer and a shallow trench formed therein. A liner oxide layer is formed on the sidewall of the shallow trench and then a silicon nitride layer is formed conformably over the substrate. A developable material layer is formed to fill up the shallow trench. After the baking process, a part of the developable material layer is removed until the top surface of the developable material layer is lower than that of the substrate. The silicon nitride layer that is exposed by the developable material layer is removed and the remained developable material layer is removed. Following a thermal oxidation process, an insulating layer is formed over the substrate and fills up the shallow trench. After planarization and removing the mask layer, a shallow trench isolation structure is formed.

Abstract: A photomask structure is described, including a substrate having multiple half-tone phase shift patterns on a device region and multiple opaque patterns on a die seal ring region. By using the photomask, a side lobe effect does not occur to the photoresist layer corresponding to the die seal ring region in the exposure step.

Abstract: The invention is directed to a method for determining an overlay correlation set between two successive patterned material layers on a substrate. The method comprises steps of providing a first material layer having a first overlay mark formed therein over the substrate and then using an exposure tool with a first overlay correlation set to form a patterned photoresist layer on the first material layer, wherein the patterned photoresist layer comprises a mark pattern and the mark pattern is located over the first overlay mark for defining a later formed second material layer on the first material layer to be a second overlay mark. Thereafter, a pre-process metrology overlay parameter set between the first overlay mark and the mark pattern is obtained. The first overlay correlation set at the exposure tool is adjusted according to the pre-process metrology overlay parameter set.

Abstract: The invention is directed to a mark pattern for forming a process monitor mark in a patterned underlayer to monitor a patterning result of a photoresist layer over the patterned underlayer around the boundary between a peripheral region and a device region of a die, wherein the patterned underlayer is formed by using a first mask having a first pattern in a main region of the first mask and the mark pattern at an unused region of the first mask and the first pattern possesses a first mask critical dimension. The mark pattern comprising: a second pattern and a frame pattern. The second pattern has a second mask critical dimension, wherein the second mask critical dimension is as same as the first mask critical dimension. The frame pattern encloses the second pattern.

Abstract: A mixing-and-matching method for an optical environment group. The optical environment group has at least a primary optical environment having a first numerical aperture (NA) and a first off-axis illumination (OAI) mode and at least one backup optical environment having a second NA and a second OAI mode. The method comprises steps of providing information including a first critical dimension behavior on a mask (a first MCD behavior) with respect to a design rule and a first critical dimension behavior on a developed photoresist (a first DCD behavior) obtained by using the primary optical environment with the mask and modifying the first MCD behavior to be a second MCD behavior according to the information, wherein a second DCD behavior obtained by using the backup optical environment with the modified mask having the second MCD behavior is as same as the first DCD behavior.

Abstract: A photomask for defining a photoresist layer formed on a wafer having at least an alignment mark region, wherein each alignment mark region has an alignment mark. The photomask comprises a shot region and an alignment mark pattern region. The alignment mark pattern region has a profile equal to the profile of the alignment mark region on the wafer. Further, the alignment mark pattern region comprises a block region, a clean-out region and a dummy pattern region. The position of the block region in the alignment mark pattern region is corresponding to the relative position of the alignment mark in the alignment mark region. The clean-out region is adjacent to one side of the block region and the dummy pattern region is adjacent to another side of the block region.

Abstract: The present invention discloses a mask for reducing the proximity effect. The mask comprises a plurality of line-shaped features, a plurality of first assist features positioned between the line-shaped features and a plurality of second assist features positioned between the line-shaped feature and the first assist feature. The line-shaped feature corresponds to isolation trenches to be formed on a silicon wafer. The first assist feature is rectangular in shape and has a larger width at the direction perpendicular to the line-shaped features. The width of the second assist feature is smaller than two-fifths of the wavelength but larger than one-fourth of the wavelength of an exposure source. The size of the first assist feature and the second assist feature is so designed to be non-resolvable, while the line-shaped feature is resolvable and transferred to the silicon wafer.

Abstract: A method is providing for forming a semiconductor device including providing a substrate having a photoresist layer formed thereon, and providing a photomask over at least a portion of the photoresist layer, the photomask having a main pattern and an assist pattern. The method further includes transferring the main pattern to the photoresist layer, and forming a pattern on the substrate in such a way that excessively rounded corners caused by the optical proximity effect (OPE) are reduced.

Abstract: A method is provided for forming a semiconductor device including providing a substrate having a photoresist layer formed thereon, and providing a photomask over at least a portion of the photoresist layer, the photomask having a main pattern and an assist pattern. The method further includes transferring the main pattern to the photoresist layer, and forming a pattern on the substrate in such a way that excessively rounded corners caused by the optical proximity effect (OPE) are reduced.

Abstract: A method of forming a feature pattern in a photosensitive layer includes forming the photosensitive layer on a substrate, providing a first mask having a first opaque area thereon, and performing a first exposure process with a first dose to form a first unexposed image in the photosensitive layer. The method further includes performing a second exposure process with a second dose to expose sidewalls of the first unexposed image so that the sidewalls of the first unexposed image receive at least a portion of the second dose thus forming a second unexposed image in the photosensitive layer, and developing the photosensitive layer with a developing process to form the feature pattern and to create features having smaller widths than those which would result in developing the photosensitive layer of the first unexposed image.

Abstract: A method of forming a feature pattern in a photosensitive layer includes forming the photosensitive layer on a substrate, providing a first mask having a first opaque area thereon, and performing a first exposure process with a first dose to form a first unexposed image in the photosensitive layer. The method further includes performing a second exposure process with a second dose to expose sidewalls of the first unexposed image so that the sidewalls of the first unexposed image receive at least a portion of the second dose thus forming a second unexposed image in the photosensitive layer, and developing the photosensitive layer with a developing process to form the feature pattern and to create features having smaller widths than those which would result in developing the photosensitive layer of the first unexposed image.

Abstract: A cathode ray tube of long persisting time has a control unit operably associated with a central processing unit and a CRT controller wherein the control unit generates signals to select data bus and memory access. A video inhibit signal is generated for a predetermined period of time by the control unit to avoid or prevent flicker or flashing on the screen during refreshing thereof.