Abstract: A manufacturing method of a semiconductor wafer includes forming a plurality of alignment trenches in the wafer substrate. A dielectric layer is formed over the substrate filling the trenches. A planarization process is performed to remove the dielectric layer above the substrate. A photolithograph process is subsequently performed to selectively remove the dielectric layer formed in the trenches in the alignment area.

Abstract: A method for checking the alignment accuracy using an overlay mark is provided. The overlay mark includes an inner mark and an outer mark formed on a wafer. The outer mark is formed in a lower layer on the wafer when the lower layer is patterned. The inner mark is formed within the outer mark over the lower layer when a lithography process for defining an upper layer is performed. A measurement process is conducted to obtain a first relation between each of the interior profiles of the outer marks and a second relation between each of the inner marks. Alternatively, a third relation between each of the interior profiles of the outer marks and each of the inner marks is obtained. The X-directional alignment accuracy and y-directional alignment accuracy are computed according to the first and the second relations, or the third relation.

Abstract: An improved photolithography method and mask are disclosed. The method exposes a substrate coated with a photosensitive material using a first mask. The photosensitive material after said first exposure includes one or more under-exposed or incompletely exposed portions or one or more portions prone to peeling. The under-exposed or incompletely exposed portions or portions prone to peeling are subjected to a second exposure using a second mask. The second mask includes a pattern for projecting an image on the substrate coated with the photosensitive material. The image corresponds to areas of the photosensitive material that have been under-exposed or incompletely exposed or areas prone to peeling.

Abstract: A photomask for defining a photoresist layer formed on a wafer having at least an alignment mark region, wherein each alignment mark region has an alignment mark. The photomask comprises a shot region and an alignment mark pattern region. The alignment mark pattern region has a profile equal to the profile of the alignment mark region on the wafer. Further, the alignment mark pattern region comprises a block region, a clean-out region and a dummy pattern region. The position of the block region in the alignment mark pattern region corresponds to the relative position of the alignment mark in the alignment mark region. The clean-out region is adjacent to one side of the block region and the dummy pattern region is adjacent to another side of the block region.

Abstract: A method for forming a shallow trench isolation (STI) structure is provided. A pad oxide layer and a nitride silicon layer are formed on a provided substrate sequentially. The pad oxide layer, the nitride silicon layer and the substrate are then etched to form a trench. An oxide liner and a nitride liner are formed in the trench. A self-align photo process is implemented and the nitride liner is then etched to expose the oxide liner.

Abstract: A mask for producing an image feature on an image surface during a semiconductor fabrication process is provided, the mask comprising a main feature having opaque areas and transmissive areas arranged in the form of the image feature, wherein each end of the main feature includes at least one of an opaque edge and a transmissive edge, wherein the opaque edge includes a set of transmissive assist features arranged therein such that the set of transmissive assist features align alternately with the transmissive areas of the main feature, and the transmissive edge includes a set of opaque assist features arranged therein such that the set of opaque assist features align alternately with the opaque areas of the main feature.

Abstract: The invention is directed to an overlay mark in a first material layer in an overlay alignment region of a wafer and the first material layer is made from a first material. The overlay mark includes a plurality of mark regions and each of the mark regions comprises a plurality mark elements embedded in the first material layer. Each of the mark elements is made of a second material different from the first material of the first material layer and the mark elements evenly distribute in the mark region.

Abstract: The invention is directed to a method for patterning a material layer. The method comprises steps of forming a first mask layer on the material layer and then patterning the first mask layer. The patterned first mask layer has a pattern therein and a plurality of gaps within the patterns and the gaps expose a portion of the material layer. Further, a second mask layer is formed over the material layer and the second mask layer fills the gaps. An interface layer is formed between the patterned first mask layer and the second mask layer. A portion of the second material layer is removed until the top surface of the interface layer is exposed. The interface layer is removed to expose a portion of the material layer and the material layer is patterned by using the patterned first mask layer and the second mask layer as a mask.

Abstract: The invention is directed to a method for patterning a material layer. The method comprises steps of forming a mask layer on the material layer. A multiple patterning process is performed on the mask layer for transferring at least a first pattern from a first photomask through a first photoresist and a second pattern from a second photomask from a second photoresist layer into the mask layer without performing any etching process. The mask layer exposes a portion of the material layer and the mask layer is patterned at the time that the first photoresist layer and the second photoresist layer are developed respectively. An etching process is performed to pattern the material layer by using the mask layer as an etching mask.

Abstract: The invention is directed to an alignment mark in a material layer in an alignment region of a wafer. The alignment mark comprises a plurality of sub-marks. Each of the sub-mark comprises a first element and a plurality of second elements. The second elements are embedded in the first element and a first top surface of the first element is at the same height as a second top surface of each of the second elements.

Abstract: A method of forming a mark in an IC fabricating process is described. Two parts of the mark each including a plurality of linear patterns are respectively defined by two exposure steps that either belong to two lithography processes respectively or constitute a double-exposure process including X-dipole and Y-dipole exposure steps.

Abstract: A mixing-and-matching method for an optical environment group is disclosed in this invention. The optical environment group has at least a primary optical environment having a first numerical aperture (NA) and a first off-axis illumination (OAI) mode and at least one backup optical environment having a second NA and a second OAI mode. The method comprises steps of providing information including a first critical dimension behavior on a mask (a first MCD behavior) with respect to a design rule and a first critical dimension behavior on a developed photoresist (a first DCD behavior) obtained by using the primary optical environment with the mask and modifying the first MCD behavior to be a second MCD behavior according to the information, wherein a second DCD behavior obtained by using the backup optical environment with the modified mask having the second MCD behavior is as same as the first DCD behavior.

Abstract: A method of enabling alignment of a wafer in at least one exposure step of an integrated circuit process after a UV-blocking metal layer is formed over the whole wafer covering a patterned upmost metal layer of the integrated circuit is described, wherein the wafer has an edge portion where a composite dielectric layer corresponding to the dielectric layers of the integrated circuit is formed. The method includes forming a cavity in the composite dielectric layer over the edge portion of the wafer in the patterning process of the upmost metal layer, such that an alignment mark is formed after the UV-blocking metal layer is formed.

Abstract: An overlay mark is described, wherein the overlay mark is used for checking the alignment accuracy between a lower layer defined by two exposure steps and a lithography process for defining an upper layer, including a part of the lower layer and a photoresist patter. The part of the lower layer includes two first x-directional, two first y-directional bar-like patterns. The first x-directional and first y-directional bar-like patterns are defined by one exposure step to define a first rectangle. The second x-directional and second y-directional bar-like patterns are defined by another exposure to define a second rectangle, wherein the second rectangle is wider than the first rectangle. The photoresist pattern, which is formed by the lithograph process, is disposed over the part of the lower layer and is surrounded by the bar-like patterns.

Abstract: An exposure process is described, for defining in a photoresist layer a plurality of first patterns having a first pitch and a second pattern between them that is wider than one first pattern. A first exposure step is conducted to the photoresist layer with a first photomask that has a plurality of the first patterns without a second pattern between them, wherein the first patterns on the first photomask have the first pitch only. A second exposure step is conducted to the photoresist layer with a second photomask that has a third pattern narrower than the second pattern at a position corresponding to the second pattern. The exposure dose of the first or second exposure step alone is not sufficient to define any pattern in the photoresist layer.

Abstract: Pattern registration marks which include: a substrate and an upper material layer disposed above the substrate; an outer trench formed in the upper material layer, the outer trench having an outer trench width; an inner trench formed in the upper material layer, the inner trench having an inner trench width; and a conformal layer disposed in the inner trench and the outer trench, the conformal layer having a conformal layer thickness; wherein the outer trench width is greater than twice the conformal layer thickness, and wherein the inner trench width is less than or equal to twice the conformal layer thickness; and methods of using the same.

Abstract: A photomask is provided. The photomask includes a device pattern region, a die sealing pattern region and at least two alignment mark patterns. The device pattern region has a first side and a second side and the first side is opposite to the second side. The die sealing pattern region surrounds the device pattern region. The alignment mark patterns includes a first overlay mark pattern and a second overlay mark pattern and the first overlay mark pattern and the second overlay mark pattern are located outside the device pattern region and at the first side and second side respectively. An arrangement relationship between the first overlay mark pattern and the first side is a mirror of an arrangement relationship between the second overlay mark pattern and the second side.

Abstract: An overlay mark for checking the alignment accuracy between a lower layer and a lithography process for defining an upper layer is described, including a part of the lower layer having two first x-directional trenches, two first y-directional trenches, two second x-directional trenches and two second y-directional trenches therein, and two x-directional and two y-directional photoresist bars thereover that are surrounded by the trenches and formed in the lithography process. When the lower layer is fully aligned with the lithography process, the intersection of the central line of the two first x-directional trenches and that of the two first y-directional trenches, the intersection of the central line of the two second x-directional trenches and that of the two second y-directional trenches and the intersection of the central line of the two x-directional photoresist lines and that of the two y-directional photoresist lines coincide with each other.

Abstract: A method for checking the alignment accuracy using an overlay mark is provided. The overlay mark includes an inner mark and an outer mark formed on a wafer. The outer mark is formed in a lower layer on the wafer when the lower layer is patterned. The inner mark is formed within the outer mark over the lower layer when a lithography process for defining an upper layer is performed. A measurement process is conducted to obtain a first relation between each of the interior profiles of the outer marks and a second relation between each of the inner marks. Alternatively, a third relation between each of the interior profiles of the outer marks and each of the inner marks is obtained. The X-directional alignment accuracy and y-directional alignment accuracy are computed according to the first and the second relations, or the third relation.

Abstract: A photomask with alignment marks for the current layer is provided with four edges. The photomask includes main patterns, an inter-scribe lane pattern sited between the main patterns, an extra-scribe lane pattern only sited on the three edges of the photomask, a first set of alignment marks for the current layer on opposite edges having the extra-scribe lane patterns. The photomask further includes a second set of alignment marks for the current layer on opposite edges in which only one has the extra-scribe lane pattern, and they are placed on opposite locations in the inter-scribe lane pattern and the extra-scribe lane pattern, respectively. Moreover, each one of the second set of alignment marks for the current layer include multiple parallel patterns and at least one vertical pattern sited on at least one end of the parallel patterns which are parallel to an extended direction of the opposite edges.