Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a magnetic shielding layer. The two magnetic tunnel junction elements are arranged side by side. The magnetic shielding layer is disposed between the magnetic tunnel junction elements. A method of forming said magnetic tunnel junction (MTJ) device includes the following steps. An interlayer including a magnetic shielding layer is formed. The interlayer is etched to form recesses in the interlayer. The magnetic tunnel junction elements fill in the recesses. Or, a method of forming said magnetic tunnel junction (MTJ) device includes the following steps. A magnetic tunnel junction layer is formed. The magnetic tunnel junction layer is patterned to form magnetic tunnel junction elements. An interlayer including a magnetic shielding layer is formed between the magnetic tunnel junction elements.

Abstract: An integrated circuit device includes a complementary metal oxide semiconductor (CMOS) image sensor. The complementary metal oxide semiconductor (CMOS) image sensor includes a P-N junction photodiode, a transistor gate, a polysilicon plug and a stacked metal layer. The P-N junction photodiode is disposed in a substrate. The transistor gate and the polysilicon plug are disposed on the substrate, wherein the polysilicon plug is directly connected to the P-N junction photodiode. The stacked metal layer connects the polysilicon plug to the transistor gate, wherein the stacked metal layer includes a lower metal layer and an upper metal layer, and the lower metal layer includes a first metal silicide part contacting to the polysilicon plug. The present invention also provides a method of fabricating said integrated circuit device.

Abstract: The present invention discloses a semiconductor structure with an epitaxial layer and method of manufacturing the same. The semiconductor structure with the epitaxial layer includes a substrate, a blocking layer on the substrate, multiple recesses formed in the substrate, wherein the recess extends along <111> crystal faces of the substrate, and an epitaxial layer on the blocking layer, wherein the epitaxial layer is provided with a buried portion in each recess and a surface portion formed on the blocking layer.

Abstract: A non-volatile memory includes a back gate, a first graphene ribbon layer, a dielectric layer, a second graphene ribbon layer and a porous dielectric layer. The back gate is disposed in a substrate. The first graphene ribbon layer is disposed on the substrate. The dielectric layer covers the first graphene ribbon layer but exposes an exposed part of the first graphene ribbon layer. The second graphene ribbon layer including two end parts connected by a cantilever part is disposed above the first graphene ribbon layer, and the cantilever part is right above the exposed part of the first graphene ribbon layer. The porous dielectric layer is disposed on the dielectric layer and seals the cantilever part. The present invention also provides a method of forming said non-volatile memory.

Abstract: A semiconductor device includes an oxide semiconductor layer, disposed over a substrate. A source electrode of a metal nitride is disposed on the oxide semiconductor layer. A drain electrode of the metal nitride is disposed on the oxide semiconductor layer. A metal-nitride oxidation layer is formed on a surface of the source electrode and the drain electrode. A ratio of a thickness of the metal-nitride oxidation layer to a thickness of the drain electrode or the source electrode is equal to or less than 0.2.

Abstract: An epitaxial process applying light illumination includes the following steps. A substrate is provided. A dry etching process and a wet etching process are performed to form a recess in the substrate, wherein an infrared light illuminates while the wet etching process is performed. An epitaxial structure is formed in the recess.

Abstract: A manufacturing method of a metal-insulator-metal (MIM) capacitor structure includes the following steps. A bottom plate is formed. A first conductive layer is patterned to be the bottom plate, and the first conductive layer includes a metal element. An interface layer is formed on the first conductive layer by performing a nitrous oxide (N2O) treatment on a top surface of the first conductive layer. The interface layer includes oxygen and the metal element of the first conductive layer. A dielectric layer is formed on the interface layer. A top plate is formed on the dielectric layer. The metal-insulator-metal capacitor structure includes the bottom plate, the interface layer disposed on the bottom plate, the dielectric layer disposed on the interface layer, and the top plate disposed on the dielectric layer.

Abstract: A semiconductor device includes an oxide semiconductor layer, disposed over a substrate. A source electrode of a metal nitride is disposed on the oxide semiconductor layer. A drain electrode of the metal nitride is disposed on the oxide semiconductor layer. A metal-nitride oxidation layer is formed on a surface of the source electrode and the drain electrode. A ratio of a thickness of the metal-nitride oxidation layer to a thickness of the drain electrode or the source electrode is equal to or less than 0.2.

Abstract: An electrical chemical plating process is provided. A semiconductor structure is provided in an electrical plating platform. A pre-electrical-plating step is performed wherein the pre-electrical-plating step is carried out under a fixed voltage environment and lasts for 0.2 to 0.5 seconds after the current is above the threshold current of the electrical plating platform. After the pre-electrical-plating step, a first electrical plating step is performed on the semiconductor structure.

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a first gradient layer, two source/drain structures, a second gradient layer, and a gate. The first gradient layer is disposed on the substrate. The two source/drain structures are separately disposed on the first gradient layer. The second gradient layer is disposed on the two source/drain structures and the first gradient layer, and a second portion of the second gradient layer directly contacts a first portion of the first gradient layer. The gate is disposed on the second gradient layer, between the two source/drain structures.

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a first gradient layer, two source/drain structures, a second gradient layer, and a gate. The first gradient layer is disposed on the substrate. The two source/drain structures are separately disposed on the first gradient layer. The second gradient layer is disposed on the two source/drain structures and the first gradient layer, and a second portion of the second gradient layer directly contacts a first portion of the first gradient layer. The gate is disposed on the second gradient layer, between the two source/drain structures.

Abstract: A semiconductor device includes an oxide semiconductor layer, disposed over a substrate. A source electrode of a metal nitride is disposed on the oxide semiconductor layer. A drain electrode of the metal nitride is disposed on the oxide semiconductor layer. A metal-nitride oxidation layer is formed on a surface of the source electrode and the drain electrode. A ratio of a thickness of the metal-nitride oxidation layer to a thickness of the drain electrode or the source electrode is equal to or less than 0.2.

Abstract: A semiconductor device including a substrate, a spacer and a high-k dielectric layer having a U-shape profile is provided. The spacer located on the substrate surrounds and defines a trench. The high-k dielectric layer having a U-shape profile is located in the trench, and the high-k dielectric layer having a U-shape profile exposes an upper portion of the sidewalls of the trench.

Abstract: The present invention provides a semiconductor structure, the semiconductor structure includes a substrate defining a memory region and a transistor region, an insulating layer is disposed on the substrate, a 2D material layer disposed on the insulating layer, and disposed within the memory and the transistor region, parts of the 2D material layer within the transistor region is used as the channel region of a transistor structure, the transistor structure is disposed on the channel region. And a resistive random access memory (RRAM) located in the memory region, the RRAM includes a lower electrode layer, a resistance transition layer and an upper electrode layer being sequentially located on the 2D material layer and electrically connected to the channel region.

Abstract: A semiconductor device includes a semiconductor substrate, at least a first fin structure, at least a second fin structure, a first gate, a second gate, a first source/drain region and a second source/drain region. The semiconductor substrate has at least a first active region to dispose the first fin structure and at least a second active region to dispose the second fin structure. The first/second fin structure partially overlapped by the first/second gate has a first/second stress, and the first stress and the second stress are different from each other. The first/second source/drain region is disposed in the first/second fin structure at two sides of the first/second gate.

Abstract: A semiconductor structure includes a capacitor. The capacitor includes a bottom electrode, a first high-k dielectric layer, a second high-k dielectric layer and a top electrode. The bottom electrode includes a first layer and a second layer disposed on the first layer. The bottom electrode is formed of TiN. The first layer has a crystallization structure. The second layer has an amorphous structure. The first high-k dielectric layer is disposed on the bottom electrode. The first high-k dielectric layer is formed of TiO2. The second high-k dielectric layer is disposed on the first high-k dielectric layer. The second high-k dielectric layer is formed of a material different from TiO2. The top electrode is disposed on the second high-k dielectric layer.

Abstract: The present invention provides a capacitor structure, including a bottom plate and a top plate, wherein the top plate has a first sidewall, and wherein an area of the top plate is less than an area of the bottom plate. The capacitor structure further includes a dielectric layer in between the bottom plate and the top plate, the dielectric layer having a second sidewall, wherein the first sidewall is aligned with the second sidewall, and at least one sidewall spacer placed against the first sidewall of the top plate and the second sidewall of the dielectric layer, and overlaying a portion of the bottom plate.

Abstract: A method for fabricating a metal-insulator-metal (MIM) capacitor includes the steps of: forming a capacitor bottom metal (CBM) layer on a material layer; forming a silicon layer on the CBM layer; forming a capacitor dielectric layer on the silicon layer; and forming a capacitor top metal (CTM) layer on the capacitor dielectric layer.

Abstract: The present invention provides a non-planar FET and a method of manufacturing the same. The non-planar FET includes a substrate, a fin structure, a gate and a gate dielectric layer. The fin structure is disposed on the substrate. The fin structure includes a first portion adjacent to the substrate wherein the first portion shrinks towards a side of the substrate. The gate is disposed on the fin structure. The gate dielectric layer is disposed between the fin structure and the gate. The present invention further provides a method of manufacturing the non-planar FET.

Abstract: The present invention provides a non-planar FET and a method of manufacturing the same. The non-planar FET includes a substrate, a fin structure, a gate and a gate dielectric layer. The fin structure is disposed on the substrate. The fin structure includes a first portion adjacent to the substrate wherein the first portion shrinks towards a side of the substrate. The gate is disposed on the fin structure. The gate dielectric layer is disposed between the fin structure and the gate. The present invention further provides a method of manufacturing the non-planar FET.