Patents by Inventor Chin-Fu Lin

Chin-Fu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE HAVING METAL GATE
    Publication number: 20140106557
    Abstract: A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench; sequentially forming a high dielectric constant (high-k) gate dielectric layer and a multiple metal layer on the substrate; forming a first work function metal layer in the first gate trench; performing a first pull back step to remove a portion of the first work function metal layer from the first gate trench; forming a second work function metal layer in the first gate trench and the second gate trench; and performing a second pull back step to remove a portion of the second work function metal layer from the first gate trench and the second gate trench.
    Type: Application
    Filed: December 26, 2013
    Publication date: April 17, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ssu-I Fu, Wen-Tai Chiang, Ying-Tsung Chen, Shih-Hung Tsai, Chien-Ting Lin, Chi-Mao Hsu, Chin-Fu Lin
  • METHOD OF FORMING OPENING ON SEMICONDUCTOR SUBSTRATE
    Publication number: 20140106568
    Abstract: The present invention provides a method of forming an opening on a semiconductor substrate. First, a substrate is provided. Then a dielectric layer and a cap layer are formed on the substrate. A ratio of a thickness of the dielectric layer and a thickness of the cap layer is substantially between 15 and 1.5. Next, a patterned boron nitride layer is formed on the cap layer. Lastly, an etching process is performed by using the patterned hard mask as a mask to etch the cap layer and the dielectric layer so as to form an opening in the cap layer and the dielectric layer.
    Type: Application
    Filed: December 30, 2013
    Publication date: April 17, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Po-Chun Chen
  • Semiconductor Device Having a Metal Gate and Fabricating Method Thereof
    Publication number: 20140097507
    Abstract: The present invention provides a method of forming a semiconductor device having a metal gate. A substrate is provided and a gate dielectric and a work function metal layer are formed thereon, wherein the work function metal layer is on the gate dielectric layer. Then, a top barrier layer is formed on the work function metal layer. The step of forming the top barrier layer includes increasing a concentration of a boundary protection material in the top barrier layer. Lastly, a metal layer is formed on the top barrier layer. The present invention further provides a semiconductor device having a metal gate.
    Type: Application
    Filed: December 13, 2013
    Publication date: April 10, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chi-Mao Hsu, Hsin-Fu Huang, Chin-Fu Lin, Min-Chuan Tsai, Wei-Yu Chen, Chien-Hao Chen
  • Semiconductor device having a metal gate and fabricating method thereof
    Patent number: 8691681
    Abstract: The present invention provides a method of forming a semiconductor device having a metal gate. A substrate is provided and a gate dielectric and a work function metal layer are formed thereon, wherein the work function metal layer is on the gate dielectric layer. Then, a top barrier layer is formed on the work function metal layer. The step of forming the top barrier layer includes increasing a concentration of a boundary protection material in the top barrier layer. Lastly, a metal layer is formed on the top barrier layer. The present invention further provides a semiconductor device having a metal gate.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: April 8, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chi-Mao Hsu, Hsin-Fu Huang, Chin-Fu Lin, Min-Chuan Tsai, Wei-Yu Chen, Chien-Hao Chen
  • FABRICATING METHOD OF SHALLOW TRENCH ISOLATION STRUCTURE
    Publication number: 20140073109
    Abstract: A fabricating method of a shallow trench isolation structure includes the following steps. Firstly, a substrate is provided, wherein a high voltage device area is defined in the substrate. Then, a first etching process is performed to partially remove the substrate, thereby forming a preliminary shallow trench in the high voltage device area. Then, a second etching process is performed to further remove the substrate corresponding to the preliminary shallow trench, thereby forming a first shallow trench in the high voltage device area. Afterwards, a dielectric material is filled in the first shallow trench, thereby forming a first shallow trench isolation structure.
    Type: Application
    Filed: November 5, 2013
    Publication date: March 13, 2014
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Liang-An Huang, Yu-Chun Huang, Chin-Fu Lin, Yu-Ciao Lin, Yu-Chieh Lin, Hsin-Liang Liu, Chun-Hung Cheng, Yuan-Cheng Yang, Yau-Kae Sheu
  • Manufacturing method for semiconductor device having metal gate
    Patent number: 8669618
    Abstract: A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench; sequentially forming a high dielectric constant (high-k) gate dielectric layer and a multiple metal layer on the substrate; forming a first work function metal layer in the first gate trench; performing a first pull back step to remove a portion of the first work function metal layer from the first gate trench; forming a second work function metal layer in the first gate trench and the second gate trench; and performing a second pull back step to remove a portion of the second work function metal layer from the first gate trench and the second gate trench.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: March 11, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Ssu-I Fu, Wen-Tai Chiang, Ying-Tsung Chen, Shih-Hung Tsai, Chien-Ting Lin, Chi-Mao Hsu, Chin-Fu Lin
  • FABRICATION METHOD FOR SEMICONDUCTOR DEVICES
    Publication number: 20140065775
    Abstract: A method of fabricating a semiconductor device includes the following steps. First, a semiconductor substrate is provided, which includes at least a fin structure and at least a gate semiconductor layer disposed thereon. The gate semiconductor layer covers a portion of the fin structure. Then a sacrificial layer is deposited to cover the fin structure entirely. Subsequently, a top surface of the fin structure is exposed from the sacrificial layer through an etching process. A material layer is then deposited, which covers the gate semiconductor layer, the fin structure and the sacrificial layer conformally. Finally, the material layer is etched until the top surface of the fin structure is exposed and a first spacer is concurrently formed on side surfaces of the gate semiconductor layer.
    Type: Application
    Filed: September 5, 2012
    Publication date: March 6, 2014
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chin-Fu Lin, Chih-Chien Liu, Chia-Lin Hsu
  • Fin field-effect transistor structure and manufacturing process thereof
    Patent number: 8664055
    Abstract: A fin field-effect transistor structure includes a substrate, a fin channel and a high-k metal gate. The high-k metal gate is formed on the substrate and the fin channel. A process of manufacturing the fin field-effect transistor structure includes the following steps. Firstly, a polysilicon pseudo gate structure is formed on the substrate and a surface of the fin channel. By using the polysilicon pseudo gate structure as a mask, a source/drain region is formed in the fin channel. After the polysilicon pseudo gate structure is removed, a high-k dielectric layer and a metal gate layer are successively formed. Afterwards, a planarization process is performed on the substrate having the metal gate layer until the first dielectric layer is exposed, so that a high-k metal gate is produced.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: March 4, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Teng-Chun Tsai, Chun-Yuan Wu, Chin-Fu Lin, Chih-Chien Liu, Chin-Cheng Chien
  • MOS TRANSISTOR AND PROCESS THEREOF
    Publication number: 20140054654
    Abstract: A MOS transistor includes a gate structure on a substrate, and the gate structure includes a wetting layer, a transitional layer and a low resistivity material from bottom to top, wherein the transitional layer has the properties of a work function layer, and the gate structure does not have any work function layers. Moreover, the present invention provides a MOS transistor process forming said MOS transistor.
    Type: Application
    Filed: August 22, 2012
    Publication date: February 27, 2014
    Inventors: Ya-Hsueh Hsieh, Chi-Mao Hsu, Hsin-Fu Huang, Min-Chuan Tsai, Chien-Hao Chen, Chi-Yuan Sun, Wei-Yu Chen, Chin-Fu Lin
  • Method of forming semiconductor device
    Patent number: 8647941
    Abstract: A method of forming a semiconductor device includes the following steps. A semiconductor substrate having a first strained silicon layer is provided. Then, an insulating region such as a shallow trench isolation (STI) is formed, where a depth of the insulating region is substantially larger than a depth of the first strained silicon layer. Subsequently, the first strained silicon layer is removed, and a second strained silicon layer is formed to substitute the first strained silicon layer.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: February 11, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Teng-Chun Tsai
  • Method of forming opening on semiconductor substrate
    Patent number: 8647989
    Abstract: The present invention provides a method of forming an opening on a semiconductor substrate. First, a substrate is provided. Then a dielectric layer and a cap layer are formed on the substrate. A ratio of a thickness of the dielectric layer and a thickness of the cap layer is substantially between 15 and 1.5. Next, a patterned boron nitride layer is formed on the cap layer. Lastly, an etching process is performed by using the patterned hard mask as a mask to etch the cap layer and the dielectric layer so as to form an opening in the cap layer and the dielectric layer.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: February 11, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Po-Chun Chen
  • SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF
    Publication number: 20130334690
    Abstract: A semiconductor structure includes a work function metal layer, a (work function) metal oxide layer and a main electrode. The work function metal layer is located on a substrate. The (work function) metal oxide layer is located on the work function metal layer. The main electrode is located on the (work function) metal oxide layer. Moreover a semiconductor process forming said semiconductor structure is also provided.
    Type: Application
    Filed: June 13, 2012
    Publication date: December 19, 2013
    Inventors: Min-Chuan Tsai, Hsin-Fu Huang, Chi-Mao Hsu, Chin-Fu Lin, Chien-Hao Chen, Wei-Yu Chen, Chi-Yuan Sun, Ya-Hsueh Hsieh, Tsun-Min Cheng
  • Fabrication method and structure of through silicon via
    Patent number: 8609529
    Abstract: A method of fabricating a through silicon via (TSV) structure, in which, a patterned mask is formed on a substrate, the patterned mask has an opening, a spacer-shaped structure is formed on a sidewall of the opening, and a via hole having a relatively enlarged opening is formed by etching the spacer-shaped structure and the substrate through the opening after the spacer-shaped structure is formed. A TSV structure, in which, a via hole has an opening portion and a body portion, the opening portion is a relatively enlarged opening and has a tapered shape having an opening size of an upper portion greater than an opening size of a lower portion.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: December 17, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chin-Fu Lin, Chun-Yuan Wu, Chih-Chien Liu, Teng-Chun Tsai, Chin-Cheng Chien
  • MANUFACTURING PROCESS OF GATE STACK STRUCTURE WITH ETCH STOP LAYER
    Publication number: 20130330919
    Abstract: A manufacturing process of an etch stop layer is provided. The manufacturing process includes steps of providing a substrate; forming a gate stack structure over the substrate, wherein the gate stack structure at least comprises a dummy polysilicon layer and a barrier layer; removing the dummy polysilicon layer to define a trench and expose a surface of the barrier layer; forming a repair layer on the surface of the barrier layer and an inner wall of the trench; and forming an etch stop layer on the repair layer. In addition, a manufacturing process of the gate stack structure with the etch stop layer further includes of forming an N-type work function metal layer on the etch stop layer within the trench, and forming a gate layer on the N-type work function metal layer within the trench.
    Type: Application
    Filed: August 7, 2013
    Publication date: December 12, 2013
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Kun-Hsien LIN, Hsin-Fu Huang, Chi-Mao Hsu, Chin-Fu Lin, Chun-Yuan Wu
  • THROUGH SILICON VIA (TSV) STRUCTURE AND PROCESS THEREOF
    Publication number: 20130320537
    Abstract: A through silicon via structure is located in a recess of a substrate. The through silicon via structure includes a barrier layer, a buffer layer and a conductive layer. The barrier layer covers a surface of the recess. The buffer layer covers the barrier layer. The conductive layer is located on the buffer layer and fills the recess, wherein the contact surface between the conductive layer and the buffer layer is smoother than the contact surface between the buffer layer and the barrier layer. Moreover, a through silicon via process forming said through silicon via structure is also provided.
    Type: Application
    Filed: May 30, 2012
    Publication date: December 5, 2013
    Inventors: Jia-Jia Chen, Chi-Mao Hsu, Tsun-Min Cheng, Chun-Ling Lin, Huei-Ru Tsai, Ching-Wei Hsu, Chin-Fu Lin, Hsin-Yu Chen
  • Non-Planar FET and Manufacturing Method Thereof
    Publication number: 20130270612
    Abstract: The present invention provides a non-planar FET which includes a substrate, a fin structure, a gate and a gate dielectric layer. The fin structure is disposed on the substrate. The fin structure includes a first portion adjacent to the substrate wherein the first portion shrinks towards a side of the substrate. The gate is disposed on the fin structure. The gate dielectric layer is disposed between the fin structure and the gate. The present invention further provides a method of manufacturing the non-planar FET.
    Type: Application
    Filed: April 16, 2012
    Publication date: October 17, 2013
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Chia-Lin Hsu
  • Method for manufacturing multi-gate transistor device
    Patent number: 8551829
    Abstract: A method for manufacturing a multi-gate transistor device includes providing a semiconductor substrate having a first patterned semiconductor layer formed thereon, sequentially forming a gate dielectric layer and a gate layer covering a portion of the first patterned semiconductor layer on the semiconductor substrate, removing a portion of the first patterned semiconductor layer to form a second patterned semiconductor layer, and performing a selective epitaxial growth process to form an epitaxial layer on a surface of the second patterned semiconductor layer.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: October 8, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Teng-Chun Tsai
  • Gate stack structure with etch stop layer and manufacturing process thereof
    Patent number: 8530980
    Abstract: A gate stack structure with an etch stop layer is provided. The gate stack structure is formed over a substrate. A spacer is formed on a sidewall of the gate stack structure. The gate stack structure includes a gate dielectric layer, a barrier layer, a repair layer and the etch stop layer. The gate dielectric layer is formed on the substrate. The barrier layer is formed on the gate dielectric layer. The barrier layer and an inner sidewall of the spacer collectively define a trench. The repair layer is formed on the barrier layer and an inner wall of the trench. The etch stop layer is formed on the repair layer.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: September 10, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Kun-Hsien Lin, Hsin-Fu Huang, Chi-Mao Hsu, Chin-Fu Lin, Chun-Yuan Wu
  • NON-PLANAR SEMICONDUCTOR STRUCTURE
    Publication number: 20130228836
    Abstract: A non-planar semiconductor structure includes a substrate, at least two fin-shaped structures, at least an isolation structure, and a plurality of epitaxial layers. The fin-shaped structures are located on the substrate. The isolation structure is located between the fin-shaped structures, and the isolation structure has a nitrogen-containing layer. The epitaxial layers respectively cover a part of the fin-shaped structures and are located on the nitrogen-containing layer. Anon-planar semiconductor process is also provided for forming the semiconductor structure.
    Type: Application
    Filed: April 24, 2013
    Publication date: September 5, 2013
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Hung Tsai, Chien-Ting Lin, Chin-Cheng Chien, Chin-Fu Lin, Chih-Chien Liu, Teng-Chun Tsai, Chun-Yuan Wu
  • METHOD FOR FILLING TRENCH WITH METAL LAYER AND SEMICONDUCTOR STRUCTURE FORMED BY USING THE SAME
    Publication number: 20130214336
    Abstract: A method for filling a trench with a metal layer is disclosed. A deposition apparatus having a plurality of supporting pins is provided. A substrate and a dielectric layer disposed thereon are provided. The dielectric layer has a trench. A first deposition process is performed immediately after the substrate is placed on the supporting pins to form a metal layer in the trench, wherein during the first deposition process a temperature of the substrate is gradually increased to reach a predetermined temperature. When the temperature of the substrate reaches the predetermined temperature, a second deposition process is performed to completely fill the trench with the metal layer.
    Type: Application
    Filed: February 21, 2012
    Publication date: August 22, 2013
    Inventors: Chi-Mao Hsu, Hsin-Fu Huang, Min-Chuan Tsai, Chien-Hao Chen, Wei-Yu Chen, Chin-Fu Lin, Jing-Gang Li, Min-Hsien Chen, Jian-Hong Su