Patents by Inventor Chin-Hung Chang

Chin-Hung Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10969991
    Abstract: A multi-chip package, a controlling method of the multi-chip package and a security chip are provided. The multi-chip package includes a memory chip and a security chip. The security chip is coupled between the memory chip and a host. The security chip includes a processing circuit. The processing circuit is for enabling a security path to input an input-output signal into the processing circuit for executing a security procedure and accessing the memory chip, if a command is received by the processing circuit and the command includes a security requirement.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: April 6, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chia-Jung Chen, Chin-Hung Chang, Ken-Hui Chen
  • Publication number: 20210057002
    Abstract: A memory device, including a secure command decoder implementing security logic configured to detect commands carrying an encrypted immediate data payload from a requesting host, authenticate the host as source of the command, decode the immediate data and perform a memory access command called for by a command portion of the decrypted immediate data upon the storage cells of the memory device using the non-command portion of the decrypted immediate data, as well as to encrypt any result from executing the command portion prior to returning the result to the requesting host, and an input/output interface for I/O data units supporting multiple hosts.
    Type: Application
    Filed: April 16, 2020
    Publication date: February 25, 2021
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chia-Jung CHEN, Chin-Hung CHANG, Ken-Hui CHEN
  • Publication number: 20210051020
    Abstract: A memory device can comprise a memory, and an interface to receive a memory command sequence. A message authentication code MAC is provided with the command sequence. Control circuits on the device include a command decoder to decode a received a command sequence and to execute an identified memory operation. A message authentication engine includes logic to compute a value of a message authentication code to be matched with the received message authentication code based on the received command sequence and a stored key. The device can store a plurality of keys associated with one or more memory zones in the memory. Logic on the device prevents completion of the memory operation identified by the command sequence if the value computed does not match the received message authentication code.
    Type: Application
    Filed: August 14, 2019
    Publication date: February 18, 2021
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chia-Jung CHEN, Chin-Hung CHANG, Kuen-Long CHANG
  • Patent number: 10911229
    Abstract: A device which can be implemented on a single packaged integrated circuit or a multichip module comprises a plurality of non-volatile memory cells, and logic to use a physical unclonable function to produce a key and to store the key in a set of non-volatile memory cells in the plurality of non-volatile memory cells. The physical unclonable function can use entropy derived from non-volatile memory cells in the plurality of non-volatile memory cells to produce a key. Logic is described to disable changes to data in the set of non-volatile memory cells, and thereby freeze the key after it is stored in the set.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: February 2, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chun-Hsiung Hung, Chin-Hung Chang
  • Patent number: 10884956
    Abstract: A memory system has a plurality of memory devices coupled with a hub in discrete and shared port arrangements. A plurality of bus lines connect the plurality of memory devices to the hub, including a first subset of bus lines connected in a point-to-point configuration between the hub and a particular memory device, and a second subset of bus lines connected to all the memory devices in the plurality of memory devices including the particular memory device. Bus operation logic is configured to use the first subset of bus lines in a first operation accessing the particular memory device while simultaneously using the second subset of bus lines in a second operation accessing a different selected memory device of the plurality of memory devices.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: January 5, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Kuen-Long Chang, Ken-Hui Chen, Chin-Hung Chang
  • Patent number: 10809925
    Abstract: A memory device comprises a memory array with I/O path and security circuitry coupled to the I/O path of the memory array. The memory device comprises control circuitry, responsive to configuration data, to invoke the security circuitry. The memory device comprises a configuration store, storing the configuration data accessible by the control circuitry to specify location and size of a security memory region in the memory array. Responsive to an external command and the configuration data, the control circuitry can be configured to invoke the security circuitry on an operation specified in the external command in response to accesses into the security memory region, or to not invoke the security circuitry in response to accesses to outside the security memory region.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: October 20, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Ken-Hui Chen, Kuen-Long Chang, Chin-Hung Chang, Yu-Chen Wang
  • Publication number: 20200242273
    Abstract: A memory chip comprises a first memory controller, a first data storage zone, a security unit and an address configuration unit. The first data storage zone is coupled to the first memory controller, and represented by a first physical address range. The security unit is coupled to the first memory controller. The address configuration unit is coupled to the first memory controller. The memory chip is configured to be coupled between a host controller and another memory chip. The another memory chip comprises a second data storage zone represented by a second physical address range. The address configuration unit records one or more relationships of a logical address range corresponding to the first physical address range and the second physical address range. The security unit is configured to encrypt and decrypt data in the first data storage zone and the second data storage zone.
    Type: Application
    Filed: December 24, 2019
    Publication date: July 30, 2020
    Inventors: Kuen-Long CHANG, Chia-Jung CHEN, Chin-Hung CHANG, Ken-Hui CHEN
  • Publication number: 20200241768
    Abstract: A memory device comprises a memory array with I/O path and security circuitry coupled to the I/O path of the memory array. The memory device comprises control circuitry, responsive to configuration data, to invoke the security circuitry. The memory device comprises a configuration store, storing the configuration data accessible by the control circuitry to specify location and size of a security memory region in the memory array. Responsive to an external command and the configuration data, the control circuitry can be configured to invoke the security circuitry on an operation specified in the external command in response to accesses into the security memory region, or to not invoke the security circuitry in response to accesses to outside the security memory region.
    Type: Application
    Filed: January 28, 2019
    Publication date: July 30, 2020
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Ken-Hui CHEN, Kuen-Long CHANG, Chin-Hung CHANG, Yu-Chen WANG
  • Publication number: 20200192824
    Abstract: A security memory device coupled to a host includes: a normal region for storing normal data; a security region for storing security data; and a memory controller, coupled to the normal region and to the security region. In response to a first command which is issued from the host and indicates the security memory device to enter a security field, the memory controller allows the host to access the security region. In the security field, the memory controller performs at least one security command set on the security region. In response to a second command which is issued from the host and indicates the security memory device to exit the security field, the memory controller prohibits the host from accessing the security region.
    Type: Application
    Filed: December 12, 2018
    Publication date: June 18, 2020
    Inventors: Yu-Chen WANG, Chia-Jung CHEN, Chin-Hung CHANG, Ken-Hui CHEN
  • Publication number: 20200186339
    Abstract: A system and method use a physical unclonable function in a PUF circuit on an integrated circuit to generate a security key, and stabilize the security key by storage in a set of nonvolatile memory cells. The stabilized security key is moved from the set of nonvolatile memory cells to a cache memory, and utilized as stored in the cache memory in a security protocol. Also, data transfer from the PUF circuit to the set of nonvolatile memory cells can be disabled after using the PUF circuit to produce the security key, at a safe time, such as after the security key has been moved from the set of nonvolatile memory cells to the cache memory.
    Type: Application
    Filed: February 18, 2020
    Publication date: June 11, 2020
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chun-Hsiung HUNG, Kuen-Long CHANG, Ken-Hui CHEN, Shih-Chang HUANG, Chin-Hung CHANG, Chen-Chia FAN
  • Patent number: 10680809
    Abstract: A system including a host and a guest device, where the guest device can be implemented on a single packaged integrated circuit or a multichip circuit and have logic to use a physical unclonable function to produce a security key. The device can include logic on the guest to provide the PUF key to the host in a secure manner. The physical unclonable function can use entropy derived from non-volatile memory cells to produce the initial key. Logic is described to disable changes to PUF data, and thereby freeze the key after it is stored in the set.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: June 9, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Kuen-Long Chang, Ken-Hui Chen, Chin-Hung Chang
  • Publication number: 20200057575
    Abstract: A multi-chip package, a controlling method of the multi-chip package and a security chip are provided. The multi-chip package includes a memory chip and a security chip. The security chip is coupled between the memory chip and a host. The security chip includes a processing circuit. The processing circuit is for enabling a security path to input an input-output signal into the processing circuit for executing a security procedure and accessing the memory chip, if a command is received by the processing circuit and the command includes a security requirement.
    Type: Application
    Filed: August 15, 2018
    Publication date: February 20, 2020
    Inventors: Chia-Jung Chen, Chin-Hung Chang, Ken-Hui Chen
  • Publication number: 20190073300
    Abstract: A nested wrap-around technology includes an address counter and associated logic for generating addresses to perform a nested wrap-around access operation. The nested wrap-around access operation may be a read or a write operation. A wrap-around section length and a wrap-around count define a wrap-around block. A wrap starting address, initially set to a supplied start address, is offset from a lower boundary of a wrap-around section. Access starts at a wrap starting address and proceeds in a wrap-around manner within a wrap-around section. After access of the address immediately preceding the wrap starting address, the wrap starting address is incremented by the wrap-around section length, or, if the wrap-around section is the last one in the wrap-around block, the wrap starting address is set to the lower boundary of the wrap-around block plus the offset. Access continues until a termination event.
    Type: Application
    Filed: November 5, 2018
    Publication date: March 7, 2019
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Kuen-Long Chang, Ken-Hui Chen, Chin-Hung Chang
  • Patent number: 10162751
    Abstract: A nested wrap-around technology includes an address counter and associated logic for generating addresses to perform a nested wrap-around access operation. The nested wrap-around access operation may be a read or a write operation. A wrap-around section length and a wrap-around count define a wrap-around block. A wrap starting address, initially set to a supplied start address, is offset from a lower boundary of a wrap-around section. Access starts at a wrap starting address and proceeds in a wrap-around manner within a wrap-around section. After access of the address immediately preceding the wrap starting address, the wrap starting address is incremented by the wrap-around section length, or, if the wrap-around section is the last one in the wrap-around block, the wrap starting address is set to the lower boundary of the wrap-around block plus the offset. Access continues until a termination event.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: December 25, 2018
    Assignee: Macronix International Co., Ltd.
    Inventors: Kuen-Long Chang, Ken-Hui Chen, Chin-Hung Chang
  • Publication number: 20180278418
    Abstract: A system including a host and a guest device, where the guest device can be implemented on a single packaged integrated circuit or a multichip circuit and have logic to use a physical unclonable function to produce a security key. The device can include logic on the guest to provide the PUF key to the host in a secure manner. The physical unclonable function can use entropy derived from non-volatile memory cells to produce the initial key. Logic is described to disable changes to PUF data, and thereby freeze the key after it is stored in the set.
    Type: Application
    Filed: May 21, 2018
    Publication date: September 27, 2018
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Kuen-Long CHANG, Ken-Hui CHEN, Chin-Hung CHANG
  • Publication number: 20180176012
    Abstract: A device which can be implemented on a single packaged integrated circuit or a multichip module comprises a plurality of non-volatile memory cells, and logic to use a physical unclonable function to produce a key and to store the key in a set of non-volatile memory cells in the plurality of non-volatile memory cells. The physical unclonable function can use entropy derived from non-volatile memory cells in the plurality of non-volatile memory cells to produce a key. Logic is described to disable changes to data in the set of non-volatile memory cells, and thereby freeze the key after it is stored in the set.
    Type: Application
    Filed: January 8, 2018
    Publication date: June 21, 2018
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chun-Hsiung HUNG, Chin-Hung CHANG
  • Publication number: 20170308463
    Abstract: A nested wrap-around technology includes an address counter and associated logic for generating addresses to perform a nested wrap-around access operation. The nested wrap-around access operation may be a read or a write operation. A wrap-around section length and a wrap-around count define a wrap-around block. A wrap starting address, initially set to a supplied start address, is offset from a lower boundary of a wrap-around section. Access starts at a wrap starting address and proceeds in a wrap-around manner within a wrap-around section. After access of the address immediately preceding the wrap starting address, the wrap starting address is incremented by the wrap-around section length, or, if the wrap-around section is the last one in the wrap-around block, the wrap starting address is set to the lower boundary of the wrap-around block plus the offset. Access continues until a termination event.
    Type: Application
    Filed: April 26, 2016
    Publication date: October 26, 2017
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Kuen-Long Chang, Ken-Hui Chen, Chin-Hung Chang
  • Patent number: 9678829
    Abstract: An erasing method of a memory device is provided. The memory device includes a memory controller and a memory array having a first memory region and a second memory region. The first memory region and the second memory region share the same well. The erasing method comprising steps of: erasing the first memory region; and selectively programming the second memory region according to an error correction code algorithm.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: June 13, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chin-Hung Chang, Chia-Feng Cheng, Yu-Chen Wang, Ken-Hui Chen, Kuen-Long Chang
  • Patent number: 9672881
    Abstract: A memory device includes a variable strobe interface configured to select one of a data queue strobe signal or a system clock signal to signal initiation of data receipt at the memory device.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: June 6, 2017
    Assignee: Macronix International Co., Ltd.
    Inventors: Ken-Hui Chen, Kuen Long Chang, Chin-Hung Chang
  • Publication number: 20170109297
    Abstract: A memory system has a plurality of memory devices coupled with a hub in discrete and shared port arrangements. A plurality of bus lines connect the plurality of memory devices to the hub, including a first subset of bus lines connected in a point-to-point configuration between the hub and a particular memory device, and a second subset of bus lines connected to all the memory devices in the plurality of memory devices including the particular memory device. Bus operation logic is configured to use the first subset of bus lines in a first operation accessing the particular memory device while simultaneously using the second subset of bus lines in a second operation accessing a different selected memory device of the plurality of memory devices.
    Type: Application
    Filed: July 20, 2016
    Publication date: April 20, 2017
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Kuen-Long Chang, Ken-Hui Chen, Chin-Hung Chang