Patents by Inventor Chin-Hung Chang
Chin-Hung Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140062543Abstract: A circuit usable as a word line driver includes a driver that switches in response to a voltage on a control node, and a circuit supplying a voltage to the control node. The circuit that applies a voltage to control node provides a first static current tending to pull the control node up to a first source voltage, and provides a fighting current pulse in response to a signal selecting the driver to pull the control node down to a second source voltage, overcoming the first static current. In addition, a circuit provides a pull-up boost current on a transition of the signal selecting the driver that turns off the fighting current, and applies a boosting current pulse to the control node to assist pulling the control node quickly to the first source voltage.Type: ApplicationFiled: September 5, 2012Publication date: March 6, 2014Applicant: Macronix International Co., Ltd.Inventors: Chang-Ting Chen, Chin-Hung Chang, Shang-Chi Yang, Kuan-Ming Lu, Ken-Hui Chen, Kuen-Long Chang, Chun-Hsiung Hung
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Publication number: 20130242665Abstract: A nonvolatile memory array has a multiple erase procedures of different durations. A block of memory cells of the array can be erased by one of the different erase procedures.Type: ApplicationFiled: June 28, 2012Publication date: September 19, 2013Applicant: Macronix International Co., Ltd.Inventors: Chun-Hsiung Hung, Kuen-Long Chang, Ken-Hui Chen, Nai-Ping Kuo, Chin-Hung Chang, Chang-Ting Chen
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Patent number: 8363505Abstract: A two transistor word line driver is disclosed. An example disclosed word line driver is simplified with common signals on the gates of the p-type and the n-type transistors. An example disclosed word line driver consumes less power by applying a negative voltage to a word line driver selected from multiple word line drivers.Type: GrantFiled: May 21, 2010Date of Patent: January 29, 2013Assignee: Macronix International Co., Ltd.Inventors: Chin-Hung Chang, Wen-Chiao Ho, Chun-Hsiung Hung
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Patent number: 8347185Abstract: A method for checking reading errors of a memory includes the following steps. A first data fragment is received. A first count index according to the first data fragment is generated, wherein the first count index is corresponding to a quantity of one kind of binary value in the first data fragment. The first data fragment is written into the memory. The first data fragment is read from the memory as a second data fragment. A second count index is generated according to the second data fragment. The first count index is compared with the second count index.Type: GrantFiled: April 26, 2012Date of Patent: January 1, 2013Assignee: Macronix International Co., Ltd.Inventors: Wen-Chiao Ho, Chin-Hung Chang, Chun-Hsiung Hung, Kuen-Long Chang
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Patent number: 8270223Abstract: A memory device includes a memory sector including a memory sector, a row of select transistors and a number of drivers. The memory sector includes a plurality of word lines each couples to a plurality of memory cells. The row of select transistors select the memory sector and separate the memory sector from an immediately adjacent memory sector in the memory device. Each of the number of drivers is coupled to one of the plurality of word lines. A first one of the drivers is coupled to a first one of the word lines to receive a first control signal to conduct the first word line and a voltage source, and a second one of the drivers is coupled to a second one of the word lines to receive a second control signal to disconnect the second word line from the voltage source.Type: GrantFiled: December 1, 2009Date of Patent: September 18, 2012Assignee: Macronix International Co., Ltd.Inventors: Wen-Chiao Ho, Chin-Hung Chang, Shuo-Nan Hung, Chun-Hsiung Hung
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Publication number: 20120210193Abstract: A method for checking reading errors of a memory includes the following steps. A first data fragment is received. A first count index according to the first data fragment is generated, wherein the first count index is corresponding to a quantity of one kind of binary value in the first data fragment. The first data fragment is written into the memory. The first data fragment is read from the memory as a second data fragment. A second count index is generated according to the second data fragment. The first count index is compared with the second count index.Type: ApplicationFiled: April 26, 2012Publication date: August 16, 2012Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Wen-Chiao HO, Chin-Hung CHANG, Chun-Hsung HUNG, Kuen-Long CHANG
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Patent number: 8223559Abstract: A method of programming a memory, wherein the memory includes many memory regions having multiple multi-level cells. Each memory region includes a first bit line, a second bit line, a data buffer and a protecting unit. The protecting unit, coupled to the first and second bit lines, and the data buffer, prevents a programming error from occurring. In an embodiment of the programming method, corresponding data are inputted to the data buffers respectively. The data corresponding to an nth phase are programmed into the targeted multi-level cells. Data corresponding to an (n+1)th phase is modified to make the data corresponding to the (n+1)th phase be the same as the data corresponding to the nth phase if the targeted multi-level cells pass a programming verification process according to an nth programming verification voltage. The above steps are repeated until n is equal to a maximum, n being a positive integer.Type: GrantFiled: December 16, 2010Date of Patent: July 17, 2012Assignee: Macronix International Co., Ltd.Inventors: Wen-Chiao Ho, Chin-Hung Chang, Kuen-Long Chang, Chun-Hsiung Hung
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Patent number: 8194457Abstract: A soft program method is provided for recovering memory cells of a memory array. In an embodiment, the method includes the following steps. Memory blocks of the memory array are soft programmed with first bias voltage. A selected memory unit within a selected memory block is then soft programmed with second bias voltage. Next, whether a judging criterion is met is determined. If not, the method is repeated from the step of soft programming with the second bias voltage; if so, whether the selected unit is a last memory unit is determined. If the selected unit is not the last memory unit, other memory unit is assigned as the selected memory unit and the method is repeated from the step of soft programming with the second bias voltage. When the selected unit is the last memory unit, the memory array is bit-by-bit soft programmed with a third bias voltage.Type: GrantFiled: August 26, 2010Date of Patent: June 5, 2012Assignee: Macronix International Co., Ltd.Inventors: Chin-Hung Chang, Su-Chueh Lo, Chen-Chia Fan, Chia-Feng Cheng
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Patent number: 8190984Abstract: A method for checking reading errors of a memory includes the following steps. A first data fragment is received. A first count index according to the first data fragment is generated, wherein the first count index is corresponding to a quantity of one kind of binary value in the first data fragment. The first data fragment is written into the memory. The first data fragment is read from the memory as a second data fragment. A second count index is generated according to the second data fragment. The first count index is compared with the second count index.Type: GrantFiled: March 23, 2011Date of Patent: May 29, 2012Assignee: Macronix International Co., Ltd.Inventors: Wen-Chiao Ho, Chin-Hung Chang, Chun-Hsiung Hung, Kuen-Long Chang
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Publication number: 20120092940Abstract: A read operation for a memory device. In response to an input address indicating to read data from a different page, a selected word line, first and second global bit lines and a selected first bit line group are precharged. A first cell current flowing through the selected word line, the first and the selected first bit line groups is generated. A first reference current flowing through the second global bit line group is generated. A first half page data is read based on the first cell current and the first reference current. The selected word line, the first and the second global bit lines are kept precharged. A second cell current flowing through the selected word line is generated. A second reference current is generated. A second half page data is read based on the second cell current and the second reference current.Type: ApplicationFiled: October 19, 2010Publication date: April 19, 2012Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chin-Hung Chang, Chia-Jung Chen, Su-Chueh Lo, Ken-Hui Chen, Kuen-Long Chang
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Publication number: 20120075943Abstract: A first redundant column is used to repair multiple defects in an array of memory cells. The defects include at least a first defect and a second defect in different main columns of a plurality of main columns in the array. However, all of the multiple defects repaired by the first redundant column are not required to be in different main columns. The array is arranged into a plurality of rows accessed by row addresses and the plurality of main columns accessed by column addresses.Type: ApplicationFiled: September 29, 2010Publication date: March 29, 2012Applicant: Macronix International Co., Ltd.Inventors: Chia-Jung Chen, Su-Chueh Lo, Chin-Hung Chang, Chen-Chia Fan, Kuen-Long Chang
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Publication number: 20120051142Abstract: A soft program method is provided for recovering memory cells of a memory array. In an embodiment, the method includes the following steps. Memory blocks of the memory array are soft programmed with first bias voltage. A selected memory unit within a selected memory block is then soft programmed with second bias voltage. Next, whether a judging criterion is met is determined. If not, the method is repeated from the step of soft programming with the second bias voltage; if so, whether the selected unit is a last memory unit is determined. If the selected unit is not the last memory unit, other memory unit is assigned as the selected memory unit and the method is repeated from the step of soft programming with the second bias voltage. When the selected unit is the last memory unit, the memory array is bit-by-bit soft programmed with a third bias voltage.Type: ApplicationFiled: August 26, 2010Publication date: March 1, 2012Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chin-Hung Chang, Su-Chueh Lo, Chen-Chia Fan, Chia-Feng Cheng
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Publication number: 20110149675Abstract: A two transistor word line driver is disclosed. An example disclosed word line driver is simplified with common signals on the gates of the p-type and the n-type transistors. An example disclosed word line driver consumes less power by applying a negative voltage to a word line driver selected from multiple word line drivers.Type: ApplicationFiled: May 21, 2010Publication date: June 23, 2011Applicant: Macronix International Co., Ltd.Inventors: Chin-Hung Chang, Wen-Chiao Ho, Chun-Hsiung Hung
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Publication number: 20110128786Abstract: A memory device includes a memory sector including a memory sector, a row of select transistors and a number of drivers. The memory sector includes a plurality of word lines each couples to a plurality of memory cells. The row of select transistors select the memory sector and separate the memory sector from an immediately adjacent memory sector in the memory device. Each of the number of drivers is coupled to one of the plurality of word lines, wherein a first one of the drivers is coupled to a first one of the word lines to receive a first control signal to conduct the first word line and a voltage source, and a second one of the drivers is coupled to a second one of the word lines to receive a second control signal to disconnect the second word line from the voltage source.Type: ApplicationFiled: December 1, 2009Publication date: June 2, 2011Inventors: Wen-Chiao Ho, Chin-Hung Chang, Shuo-Nan Hung, Chun-Hsiung Hung
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Publication number: 20110085380Abstract: A method of programming a memory, wherein the memory includes many memory regions having multiple multi-level cells. Each memory region includes a first bit line, a second bit line, a data buffer and a protecting unit. The protecting unit, coupled to the first and second bit lines, and the data buffer, prevents a programming error from occurring. In an embodiment of the programming method, corresponding data are inputted to the data buffers respectively. The data corresponding to an nth phase are programmed into the targeted multi-level cells. Data corresponding to an (n+1)th phase is modified to make the data corresponding to the (n+1)th phase be the same as the data corresponding to the nth phase if the targeted multi-level cells pass a programming verification process according to an nth programming verification voltage. The above steps are repeated until n is equal to a maximum, n being a positive integer.Type: ApplicationFiled: December 16, 2010Publication date: April 14, 2011Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Wen-Chiao Ho, Chin-Hung Chang, Kuen-Long Chang, Chun-Hsiung Hung
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Patent number: 7925960Abstract: A method for checking reading errors of a memory includes receiving a first data fragment and accordingly generating a first ECC and a first count index; writing the first data fragment, the first ECC and the first count index into a memory; reading the first data fragment from the memory as a second data fragment, generating a second ECC and second count index according to the second data fragment; determining whether the first count index and second count index are equal; determining whether the first ECC and the second ECC are equal; and outputting the second data fragment when the first count index is equal to the second count index and the first ECC is equal to the second ECC.Type: GrantFiled: March 26, 2007Date of Patent: April 12, 2011Assignee: Macronix International Co., Ltd.Inventors: Wen-Chiao Ho, Chin-Hung Chang, Chun-Hsiung Hung, Kuen-Long Chang
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Patent number: 7889572Abstract: A memory includes many memory regions each including a target memory cell, a source line, a bit line and a reading control circuit. The source line is coupled to a first terminal of the target memory cell. The bit line is coupled to a second terminal of the target memory cell. The reading control circuit is for selectively applying a working voltage to the source line.Type: GrantFiled: September 4, 2008Date of Patent: February 15, 2011Assignee: Macronix International Co., Ltd.Inventors: Wen-Chiao Ho, Chin-Hung Chang, Kuen-Long Chang, Chun-Hsiung Hung
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Patent number: 7869276Abstract: A memory includes many memory regions. The memory regions have multiple multi-level cells. Each memory region includes a first bit line, a second bit line, a data buffer and a protecting unit. The first bit line is coupled to a first column of the multi-level cells. The second bit line is coupled to a second column of the multi-level cells. The data buffer is coupled to the first bit line and the second bit line and for storing data to be programmed into the multi-level cells. The protecting unit is coupled to the first bit line, the second bit line and the data buffer and is for preventing a programming error from occurring.Type: GrantFiled: November 29, 2007Date of Patent: January 11, 2011Assignee: Macronix International Co., Ltd.Inventors: Wen-Chiao Ho, Chin-Hung Chang, Kuen-Long Chang, Chun-Hsiung Hung
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Publication number: 20100192039Abstract: A method for operating a memory device is provided and includes the following steps. A first error correction code is generated according to user data. Then, the user data is written to the memory device. Moreover, the user data in the memory device is read, and a second error correction code is generated according to the read user data. Further, the first and the second error correction codes are written to the memory device.Type: ApplicationFiled: January 23, 2009Publication date: July 29, 2010Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Wen-Chiao Ho, Chin-Hung Chang, Shuo-Nan Hung, Chun-Hsiung Hung
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Patent number: 7755945Abstract: A page buffer and method of programming and reading a memory are provided. The page buffer includes a first latch, a second latch, a data change unit and a program control unit. The first latch includes a first terminal for loading data of the lower page and the upper page. The second latch includes a first terminal for storing the data of the lower page and the upper page from the first latch. The data change unit is coupled to a second terminal of the first latch for changing a voltage of the second terminal of the first latch to a low level. The program control unit is coupled to the first terminal of the second latch and the cells, and controlled by the voltage of the first terminal of the first latch for respectively programming the data of the lower page and the upper page to a target cell.Type: GrantFiled: July 30, 2008Date of Patent: July 13, 2010Assignee: Macronix International Co., Ltd.Inventors: Wen-Chiao Ho, Chin-Hung Chang, Kuen-Long Chang, Chun-Hsiung Hung