Abstract: This invention relates to a pectin-modified resistant starch prepared by cross-linking starch with pectin by pectinesterase reaction. Such resistant starch is low amylase digestible and thus is useful in food products, including nutritional supplements, to reduce calorie content and increase fiber content. This invention also relates to a composition containing the resistant starch and a process for the preparation of the same.

Abstract: A method for testing a memory includes the following steps. First, data is read from the memory and stored to a first temporary memory. Meanwhile, expected data corresponding to the data from the memory is written into a second temporary memory from a tester. Thereafter, the data in the first temporary memory and the expected data in the second temporary memory are compared with each other to judge whether the memory has an enough operation window.

Abstract: A memory includes many memory regions each including a target memory cell, a source line, a bit line and a reading control circuit. The source line is coupled to a first terminal of the target memory cell. The bit line is coupled to a second terminal of the target memory cell. The reading control circuit is for selectively applying a working voltage to the source line.

Abstract: A page buffer and method of programming and reading a memory are provided. The page buffer includes a first latch, a second latch, a data change unit and a program control unit. The first latch includes a first terminal for loading data of the lower page and the upper page. The second latch includes a first terminal for storing the data of the lower page and the upper page from the first latch. The data change unit is coupled to a second terminal of the first latch for changing a voltage of the second terminal of the first latch to a low level. The program control unit is coupled to the first terminal of the second latch and the cells, and controlled by the voltage of the first terminal of the first latch for respectively programming the data of the lower page and the upper page to a target cell.

Abstract: A clock synchronizing circuit applied in a SMD block is provided. The clock synchronizing circuit includes a number of stages of clock synchronizing units. The clock synchronizing circuit can achieve the purpose of clock synchronizing by using a novel circuit design of the forward delay unit, the mirror control unit or the backward delay unit in each stage of clock synchronizing unit or by using a short-pulse generation circuit to generate a short pulse for triggering out an output clock of each stage of forward delay unit.

Abstract: A method for programming a plurality of multi-level memory cells described herein includes iteratively changing a bias voltage applied to a first memory cell to program the first memory cell to a first threshold state and detecting when the first cell reaches a predetermined threshold voltage. The bias voltage applied to the first memory cell upon reaching the predetermined threshold voltage is recorded. A second memory cell is programmed to a second threshold state by applying an initial bias voltage to the second memory cell which is function of the recorded bias voltage.

Abstract: An auto-focusing lens of a camera includes a lens unit (11), a permanent magnet (12) being fixedly mounted around the lens unit to move with the lens unit, a first coil seat (15a) arranged on a first side of the magnet with a first winding (14a) wound thereon, and a second coil seat (15b) arranged on a second side opposite to the first side of the magnet with a second winding (14b) wound thereon. The first and second windings and the first and second coil seats are provided for establishing magnetic fields when electric currents are applied to the first and second windings. The magnetic fields interact with the magnetic field of the permanent magnet to drive the lens unit into movement between its front focus point (A) and its rear focus point (B).

Abstract: A method for programming a virtual ground array memory, which includes a first cell and a second cell adjacent to first cell, includes the following steps. First, the first cell is selected as a target cell, wherein the second cell has been programmed to have data. Next, the second cell is read and the data is recorded in a register. Then, the target cell is programmed. Next, a program verifying operation is performed on the second cell. Afterwards, the data recorded in the register is programmed back to the second cell when the program verifying operation performed on the second cell fails.

Abstract: A method for determining read voltage margins in a memory array compares as-read sum codes generated from data read from the memory array with expected sum codes generated from the loaded data. The read voltage (Vt) is stepped and the as-read sum codes are compared to the expected sum codes to determine the Vt range(s) that provides matching sum codes. Multiple read voltage margins (i.e. the read voltage margins between multiple programming levels of the MLC memory array) are determined in a parallel fashion as Vt is stepped across its range.

Abstract: A clock synchronizing circuit applied in a SMD block is provided. The clock synchronizing circuit includes a number of stages of clock synchronizing units. The clock synchronizing circuit can achieve the purpose of clock synchronizing by using a novel circuit design of the forward delay unit, the mirror control unit or the backward delay unit in each stage of clock synchronizing unit or by using a short-pulse generation circuit to generate a short pulse for triggering out an output clock of each stage of forward delay unit.

Abstract: A method for programming a plurality of multi-level memory cells described herein includes iteratively changing a bias voltage applied to a first memory cell to program the first memory cell to a first threshold state and detecting when the first cell reaches a predetermined threshold voltage. The bias voltage applied to the first memory cell upon reaching the predetermined threshold voltage is recorded. A second memory cell is programmed to a second threshold state by applying an initial bias voltage to the second memory cell which is function of the recorded bias voltage.

Abstract: A memory includes many memory regions. The memory regions have multiple multi-level cells. Each memory region includes a first bit line, a second bit line, a data buffer and a protecting unit. The first bit line is coupled to a first column of the multi-level cells. The second bit line is coupled to a second column of the multi-level cells. The data buffer is coupled to the first bit line and the second bit line and for storing data to be programmed into the multi-level cells. The protecting unit is coupled to the first bit line, the second bit line and the data buffer and is for preventing a programming error from occurring.

Abstract: This invention relates to a pectin-modified resistant starch prepared by cross-linking starch with pectin by pectinesterase reaction. Such resistant starch is low amylase digestible and thus is useful in food products, including nutritional supplements, to reduce calorie content and increase fiber content. This invention also relates to a composition containing the resistant starch and a process for the preparation of the same.

Abstract: A method for testing a memory includes the following steps. First, data is read from the memory and stored to a first temporary memory. Meanwhile, expected data corresponding to the data from the memory is written into a second temporary memory from a tester. Thereafter, the data in the first temporary memory and the expected data in the second temporary memory are compared with each other to judge whether the memory has an enough operation window.

Abstract: A method for programming a virtual ground array memory, which includes a first cell and a second cell adjacent to first cell, includes the following steps. First, the first cell is selected as a target cell, wherein the second cell has been programmed to have data. Next, the second cell is read and the data is recorded in a register. Then, the target cell is programmed. Next, a program verifying operation is performed on the second cell. Afterwards, the data recorded in the register is programmed back to the second cell when the program verifying operation performed on the second cell fails.

Abstract: A method for performing an erase operation is disclosed in a non-volatile memory having a plurality of memory cells. At least one memory cell is programmed having a threshold voltage level in a first region before programming, and after programming the memory cell has a threshold voltage level in a second region, wherein the second region is higher in threshold voltage than the fist region. The erasing operation implements a programming of memory bits that can inject negative charge carriers or electrons into a memory cell instead of using the conventional technique of injecting hot holes into the memory cell. This can avoid room temperature drift and charge loss caused by hot hole injection.

Abstract: The present invention provides a novel method in altering the sequence of multi-level-cell programming in a multi-bit-cell of a nitride trapping memory cell that reduces or eliminates voltage threshold shifts between program steps while avoiding the suppression in the duration of a read window caused by a complementary bit disturbance. In a first embodiment, the present invention programs the multi-level cell in a multi-bit-cell having four bits in the following order: programming a third program level (level3), programming a first program level (level1) and a second program level (level2) to level 1, and programming the second program level from the first program level. In a second embodiment, the present invention programs the multi-level cell in the multi-bit-cell having four bits in the following order: programming a third program level (level3), programming a second program level (level2), and programming a first program level (level1).

Abstract: A method for operating a multi-level cell (“MLC”) memory array of an integrated circuit (“IC”) programs first data into a first plurality of MLCs in the MLC memory array at a first programming level. Threshold voltages for the first plurality of MLCs are sensed, and an adjust code is set according to the threshold voltages. Second data is programmed into a second plurality of MLCs in the MLC memory array at a second programming level, the second plurality of MLCs having a program-verify value set according to the adjust code. In a further embodiment, a reference voltage for reading the second plurality of MLCs is set according to the adjust code.

Abstract: A method for performing an erase operation is disclosed in a non-volatile memory having a plurality of memory cells. At least one memory cell is programmed having a threshold voltage level in a first region before programming, and after programming the memory cell has a threshold voltage level in a second region, wherein the second region is higher in threshold voltage than the fist region. The erasing operation implements a programming of memory bits that can inject negative charge carriers or electrons into a memory cell instead of using the conventional technique of injecting hot holes into the memory cell. This can avoid room temperature drift and charge loss caused by hot hole injection.

Abstract: A page mode program sequence is described that includes first and second bias applying cycles. In the first cycle, a program bias is applied to a first part of a page of memory cells, while a program verify bias is applied to, and data is sensed from, a second part of the page. In this manner, a first part of the page is programmed, while a second part of the page is verified. This operation is followed by a second bias applying cycle, in which a program bias is applied to the second part of the page, while a program verify bias is applied to, and data is sensed from, the first part of the page.