Patents by Inventor Chin Hung
Chin Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230326806Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, a first isolation structure on the SDB structure, a shallow trench isolation (STI) adjacent to the SDB structure, and a second isolation structure on the STI. Preferably, the first isolation structure further includes a cap layer on the SDB structure and a dielectric layer on the cap layer.Type: ApplicationFiled: June 14, 2023Publication date: October 12, 2023Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chi-Ting Wu, Chin-Hung Chen, Yu-Hsiang Lin
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Publication number: 20230327003Abstract: A method for fabricating semiconductor device includes: forming a first semiconductor layer and an insulating layer on a substrate; removing the insulating layer and the first semiconductor layer to form openings; forming a second semiconductor layer in the openings; and patterning the second semiconductor layer, the insulating layer, and the first semiconductor layer to form fin-shaped structures.Type: ApplicationFiled: June 6, 2023Publication date: October 12, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chin-Hung Chen, Ssu-I Fu, Chih-Kai Hsu, Chia-Jung Hsu, Yu-Hsiang Lin
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Publication number: 20230326805Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion; forming a first gate structure on the SDB structure; forming an interlayer dielectric (ILD) layer around the first gate structure; transforming the first gate structure into a first metal gate; removing the first metal gate to form a first recess; and forming a dielectric layer in the first recess.Type: ApplicationFiled: June 14, 2023Publication date: October 12, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chi-Ting Wu, Chin-Hung Chen, Yu-Hsiang Lin
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Patent number: 11781567Abstract: A centrifugal fan is disclosed and includes a housing, a fan wheel, a first throat portion and a second throat portion. The housing includes a lower cover connected to an upper cover through a peripheral wall to form an accommodation space and an outlet. The upper cover includes an inlet communicated with the outlet. The fan wheel is disposed on the lower cover and accommodated in the accommodation space. The fan wheel is rotated along a rotation direction. The first throat portion is disposed adjacent to a lateral end of the outlet and protrudes from the peripheral wall toward the accommodation space. The second throat portion is disposed adjacent to another lateral end of the outlet, and protrudes from the peripheral wall toward the accommodation space. When the fan wheel is rotated along the rotational direction, an airflow is guided from the first throat portion to the second throat portion.Type: GrantFiled: September 22, 2022Date of Patent: October 10, 2023Assignee: DELTA ELECTRONICS, INC.Inventors: Chin-Hung Lee, Chih-Wei Chan, Ya-Ting Chang
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Publication number: 20230315340Abstract: A memory device includes a command decoder that implements security logic to detect a command sequence to read a security region of a memory array with continuous encrypted data and to output/input specific contexts for the data. Output/input of specific contexts can be during a dummy cycle to achieve greater performance. A host interfacing can, for example, execute a single command to both get the encrypted data and specific contexts that were used to encrypt the data. Our technology can implement transferring data on the system bus in ciphertext and encrypted by a different Nonce or a different session key than used in a previous transfer operation. In this way, data will be represented with different ciphertext on the bus at different sessions; thereby defending against a replay attack.Type: ApplicationFiled: May 25, 2022Publication date: October 5, 2023Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chia-Jung CHEN, Chin-Hung CHANG, Ken-Hui CHEN
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Patent number: 11763867Abstract: A memory device comprises an array of memory cells, a physically unclonable function PUF circuit in the memory device to generate a PUF code, a data path connecting a first circuit to a second circuit in the memory device coupled to the array of memory cells, and logic circuitry to encode data on the data path from the first circuit using the PUF code to produce encoded data, and to provide the encoded data to the second circuit.Type: GrantFiled: June 7, 2022Date of Patent: September 19, 2023Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chin-Hung Chang, Chia-Jung Chen, Ken-Hui Chen, Kuen-Long Chang
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Publication number: 20230282969Abstract: An electronic device is provided. The electronic device includes a substrate, a conductive layer, an insulating layer, and a modulating material. The conductive layer is disposed on the substrate and has a first opening penetrating through the conductive layer. The insulating layer is disposed on the conductive layer and includes a second opening penetrating through the insulating layer. The first opening of the conductive layer and the second opening of the insulating layer are at least partially overlapped. The modulating material is disposed on the insulating layer.Type: ApplicationFiled: May 11, 2023Publication date: September 7, 2023Inventors: Yi-Hung LIN, Tang-Chin HUNG, Chia-Chi HO, I-Yin LI
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Publication number: 20230279868Abstract: An impeller includes a hub, an outer ring, a plurality of first blades and a plurality of second blades. The plurality of first blades are arranged around the hub at intervals. Each of the plurality of first blades passes through the outer ring, extends inward from the outer ring, and is connected to the hub. The plurality of second blades are arranged around the hub at intervals. Each of the plurality of second blades passes through the outer ring. At least one of the plurality of second blades is disposed between the plurality of first blades. A length of each of the plurality of second blades is between 10% and 45% of a length of each of the plurality of first blades.Type: ApplicationFiled: March 2, 2023Publication date: September 7, 2023Inventors: Chin-Hung Lee, Chieh-Hung Chang, Chieh-Shih Chang, Ya-Ting Chang
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Publication number: 20230268346Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate having a high-voltage (HV) region and a low-voltage (LV) region; forming a base on the HV region and fin-shaped structures on the LV region; forming a first insulating around the fin-shaped structures; removing the base, the first insulating layer, and part of the fin-shaped structures to form a first trench in the HV region and a second trench in the LV region; forming a second insulating layer in the first trench and the second trench; and planarizing the second insulating layer to form a first shallow trench isolation (STI) on the HV region and a second STI on the LV region.Type: ApplicationFiled: March 21, 2022Publication date: August 24, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chun-Ya Chiu, Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Lin, Chien-Ting Lin, Chia-Jung Hsu, Chin-Hung Chen
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Publication number: 20230268424Abstract: A method for fabricating a semiconductor device includes the steps of providing a substrate having a high-voltage (HV) region and a low-voltage (LV) region, forming first fin-shaped structures on the HV region, and then performing an oxidation process to form a gate oxide layer on and directly connecting the first fin-shaped structures. Preferably, a bottom surface of the gate oxide layer includes first bumps on the first fin-shaped structures while a top surface of the gate oxide layer includes second bumps.Type: ApplicationFiled: March 28, 2022Publication date: August 24, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chia-Jung Hsu, Ssu-I Fu, Chih-Kai Hsu, Chun-Ya Chiu, Chin-Hung Chen, Yu-Hsiang Lin, Chien-Ting Lin
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Publication number: 20230257797Abstract: A centrifugal reaction device includes: a centrifugal disk including a centrifugal shaft and at least one centrifugal holder, with the centrifugal holder disposed annularly about the centrifugal shaft; and at least one magnetic block disposed on at least one side of the centrifugal holder, wherein the centrifugal holder detachably holds a reaction tube, and the reaction tube contains magnetic beads, wherein the magnetic beads move within the reaction tube under a force of the sum of a magnetic force of the magnetic block and a centrifugal force. Therefore, a reaction mixture is blended quickly and sufficiently to facilitate a reaction. With the magnetic beads adsorbing a product, a valve of the reaction tube opens under the centrifugal force to discharge a waste liquid and reduce consumption of consumables of the reaction tube.Type: ApplicationFiled: December 1, 2020Publication date: August 17, 2023Inventor: Chin Hung WANG
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Publication number: 20230261108Abstract: The disclosure discloses a manufacturing method for high-voltage transistor. The manufacturing method comprises: providing a substrate; forming a recess in the substrate; forming an epitaxial doped structure with a first conductivity type in the recess of the substrate, wherein a top portion of the epitaxial doped structure comprises a top undoped epitaxial layer; forming a gate structure on the substrate and at least overlapping with the top undoped epitaxial layer; and forming a source/drain region with a second conductivity type in the epitaxial doped structure on a side of the gate structure. The first conductivity type is different from the second conductivity type.Type: ApplicationFiled: April 24, 2023Publication date: August 17, 2023Applicant: United Microelectronics Corp.Inventors: Chun-Ya Chiu, Chih-Kai Hsu, Chin-Hung Chen, Chia-Jung Hsu, Ssu-I Fu, Yu-Hsiang Lin
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Publication number: 20230259301Abstract: Systems, devices, methods, and circuits for managing secure writes in semiconductor devices. In one aspect, a semiconductor device includes a memory array and logic circuitry coupled to the memory array. The logic circuitry is configured to execute a secure write operation in the memory array in response to receiving encrypted information. The encrypted information includes at least one of information of data to be written, an option code, or multiple addresses in the memory array, the option code specifying a way of writing the data on at least one of the multiple addresses in the memory array.Type: ApplicationFiled: August 4, 2022Publication date: August 17, 2023Applicant: Macronix International Co., Ltd.Inventors: Chin-Hung Chang, Chia-Jung Chen, Ken-Hui Chen, Chun-Hsiung Hung
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Publication number: 20230251782Abstract: A memory device and an associated control method are provided. The memory device includes a non-volatile memory array and a memory control circuit. The non-volatile memory array includes M secured memory zones. The memory control circuit is electrically connected to the non-volatile memory array. The memory control circuit provides a set of mapping information and searches a request key in the set of mapping information. The set of mapping information represents correspondences between N access keys and the M secured memory zones. The memory control circuit acquires at least one of the M secured memory zones if the request key is one of the N access keys, and performs an access command to the at least one of the M secured memory zones. M and N are positive integers.Type: ApplicationFiled: August 5, 2022Publication date: August 10, 2023Inventors: Chin-Hung CHANG, Chia-Jung CHEN, Ken-Hui CHEN, Chun-Hsiung HUNG
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Patent number: 11721899Abstract: An example radio frequency (RF) front-end module is described, which may include a printed circuit board (PCB) including a ground plane, an RF integrated circuit (RFIC) including RF components mounted on the PCB, and an antenna array on the PCB. The antenna array may operate at a first resonant frequency in a wireless communication network. Further, the RF front-end module may include a slot defined in the ground plane to provide a second resonant frequency in the wireless communication network. The second resonant frequency is lower than the first resonant frequency.Type: GrantFiled: May 19, 2022Date of Patent: August 8, 2023Assignee: Hewlett-Packard Development Company, L.P.Inventors: Chin-Hung Ma, Chien-Pai Lai, Chih Hung Chien
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Patent number: 11721770Abstract: A manufacturing method of a semiconductor device includes the following steps. An opening is formed penetrating a dielectric layer on a semiconductor substrate. A stacked structure is formed on the dielectric layer. The stacked structure includes a first semiconductor layer partly formed in the opening and partly formed on the dielectric layer, a sacrificial layer formed on the first semiconductor layer, and a second semiconductor layer formed on the sacrificial layer. A patterning process is performed for forming a fin-shaped structure including the first semiconductor layer, the sacrificial layer, and the second semiconductor layer. An etching process is performed to remove the sacrificial layer in the fin-shaped structure. The first semiconductor layer in the fin-shaped structure is etched to become a first semiconductor wire by the etching process. The second semiconductor layer in the fin-shaped structure is etched to become a second semiconductor wire by the etching process.Type: GrantFiled: September 15, 2021Date of Patent: August 8, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chin-Hung Chen, Ssu-I Fu, Chih-Kai Hsu, Chun-Ya Chiu, Chia-Jung Hsu, Yu-Hsiang Lin
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Patent number: 11721591Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion; forming a first gate structure on the SDB structure; forming an interlayer dielectric (ILD) layer around the first gate structure; transforming the first gate structure into a first metal gate; removing the first metal gate to form a first recess; and forming a dielectric layer in the first recess.Type: GrantFiled: June 4, 2021Date of Patent: August 8, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chi-Ting Wu, Chin-Hung Chen, Yu-Hsiang Lin
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Patent number: 11712771Abstract: A power tool assembly includes a hand-held power tool, a dust collector removably coupled to the power tool, and first and second power tool battery packs each of which is interchangeably coupled with the power tool and the dust collector for separately powering the power tool and the dust collector, respectively.Type: GrantFiled: June 26, 2020Date of Patent: August 1, 2023Assignee: MILWAUKEE ELECTRIC TOOL CORPORATIONInventors: Michael R. Brewster, Tsz Kin Wong, Chin Hung Lam, Brian P. Wattenbach, Brandon L. Verbrugge, Roland Vögele, Kurt Limberg, Ming Cong Chen
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Publication number: 20230238196Abstract: A keyswitch structure includes a base plate, a keycap, and a support mechanism. The support mechanism supports the keycap above the base plate. An outer support of the support mechanism includes a reinforcing body and a connecting structure fixed on the reinforcing body. The outer support is connected to the base plate and the keycap through the connecting structure. In an embodiment, the reinforcing body has two openings. Two inner supports of the support mechanism are pivotally connected to the connecting structure and are located in the two openings, respectively. In another embodiment, the reinforcing body as a whole extends along a plane. The reinforcing body has a bent fringe, which is inserted into the connecting structure and is not perpendicular to the plane.Type: ApplicationFiled: November 3, 2022Publication date: July 27, 2023Applicant: DARFON ELECTRONICS CORP.Inventors: Chin-Hung Lin, Li-Yen Ning, Hsiao-Han Chu
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Patent number: 11710778Abstract: A method for fabricating semiconductor device includes: forming a first semiconductor layer and an insulating layer on a substrate; removing the insulating layer and the first semiconductor layer to form openings; forming a second semiconductor layer in the openings; and patterning the second semiconductor layer, the insulating layer, and the first semiconductor layer to form fin-shaped structures.Type: GrantFiled: March 10, 2021Date of Patent: July 25, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chin-Hung Chen, Ssu-I Fu, Chih-Kai Hsu, Chia-Jung Hsu, Yu-Hsiang Lin