Patents by Inventor Chin Hung

Chin Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230238196
    Abstract: A keyswitch structure includes a base plate, a keycap, and a support mechanism. The support mechanism supports the keycap above the base plate. An outer support of the support mechanism includes a reinforcing body and a connecting structure fixed on the reinforcing body. The outer support is connected to the base plate and the keycap through the connecting structure. In an embodiment, the reinforcing body has two openings. Two inner supports of the support mechanism are pivotally connected to the connecting structure and are located in the two openings, respectively. In another embodiment, the reinforcing body as a whole extends along a plane. The reinforcing body has a bent fringe, which is inserted into the connecting structure and is not perpendicular to the plane.
    Type: Application
    Filed: November 3, 2022
    Publication date: July 27, 2023
    Applicant: DARFON ELECTRONICS CORP.
    Inventors: Chin-Hung Lin, Li-Yen Ning, Hsiao-Han Chu
  • Patent number: 11710778
    Abstract: A method for fabricating semiconductor device includes: forming a first semiconductor layer and an insulating layer on a substrate; removing the insulating layer and the first semiconductor layer to form openings; forming a second semiconductor layer in the openings; and patterning the second semiconductor layer, the insulating layer, and the first semiconductor layer to form fin-shaped structures.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: July 25, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Hung Chen, Ssu-I Fu, Chih-Kai Hsu, Chia-Jung Hsu, Yu-Hsiang Lin
  • Patent number: 11705492
    Abstract: A first gate and a second gate are formed on a substrate with a gap between the first and second gates. The first gate has a first sidewall. The second gate has a second sidewall directly facing the first sidewall. A first sidewall spacer is disposed on the first sidewall. A second sidewall spacer is disposed on the second sidewall. A contact etch stop layer is deposited on the first and second gates and on the first and second sidewall spacers. The contact etch stop layer is subjected to a tilt-angle plasma etching process to trim a corner portion of the contact etch stop layer. An inter-layer dielectric layer is then deposited on the contact etch stop layer and into the gap.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: July 18, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Fan Li, Kuo-Chin Hung, Wen-Yi Teng, Ti-Bin Chen
  • Patent number: 11688934
    Abstract: An antenna device is provided. The antenna device includes a first substrate, a first conductive layer, a first insulating structure, a second substrate, a second conductive layer and a liquid-crystal layer. The first conductive layer is disposed on the first substrate. The first insulating structure is disposed on the first conductive layer, and the first insulating structure includes a first region and a second region. The second substrate is disposed opposite to the first substrate. The second conductive layer is disposed on the second substrate. The liquid-crystal layer is disposed between the first conductive layer and the second conductive layer. The thickness of the first region is less than the thickness of the second region, and at least a portion of the first region is disposed in an overlapping region of the first conductive layer and the second conductive layer.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: June 27, 2023
    Assignee: INNOLUX CORPORATION
    Inventors: Yi-Hung Lin, Tang-Chin Hung, Chia-Chi Ho, I-Yin Li
  • Publication number: 20230195671
    Abstract: A storage enclosure connected to a server via an external network and includes a network switch, an expander that is connected to the network switch and that is configured to generate enclosure data that supports a format conforming with SCSI Enclosure Services, and a board management controller (BMC) that is connected to the network switch and the expander. The BMC is configured to translate the enclosure data into enclosure translating data that supports a Redfish® format. The expander is configured to, after generating the enclosure data, transmit the enclosure data through the network switch to the BMC via an internal network. The BMC is configured to translate the enclosure data into the enclosure translating data, and to transmit the enclosure translating data to the network switch. The network switch transmits the enclosure translating data to the server through the external network.
    Type: Application
    Filed: December 14, 2022
    Publication date: June 22, 2023
    Inventors: Jyun-Jie WANG, Shao-Che CHANG, Cheng-Tung WANG, Yen-Lun TSENG, Chin-Hung TAN
  • Publication number: 20230197523
    Abstract: A method for fabricating a semiconductor device includes first providing a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate, and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is even with a top surface of the fin-shaped structure.
    Type: Application
    Filed: January 27, 2022
    Publication date: June 22, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Lin, Chien-Ting Lin, Chun-Ya Chiu, Chia-Jung Hsu, Chin-Hung Chen
  • Publication number: 20230197710
    Abstract: A method for fabricating a semiconductor device includes first providing a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate, and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is lower than a top surface of the fin-shaped structure.
    Type: Application
    Filed: January 27, 2022
    Publication date: June 22, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Lin, Chien-Ting Lin, Chia-Jung Hsu, Chun-Ya Chiu, Chin-Hung Chen
  • Publication number: 20230198141
    Abstract: An example antenna device includes an antenna array coupled to a motor. The antenna device also includes a controller to determine an antenna array direction weighting based on a weather condition and a time condition. The controller is also to cause the motor to rotate the antenna array based on the antenna array direction weighting.
    Type: Application
    Filed: April 13, 2018
    Publication date: June 22, 2023
    Inventors: CHIH-HUNG CHIEN, CHIN-HUNG MA, MIN-HSU CHUANG
  • Patent number: 11682728
    Abstract: The disclosure discloses a structure of high-voltage (HV) transistor which includes a substrate. An epitaxial doped structure with a first conductive type is formed in the substrate, wherein a top portion of the epitaxial doped structure includes a top undoped epitaxial layer. A gate structure is disposed on the substrate and at least overlapping with the top undoped epitaxial layer. A source/drain (S/D) region with a second conductive type is formed in the epitaxial doped structure at a side of the gate structure. The first conductive type is different from the second conductive type.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: June 20, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Ya Chiu, Chih-Kai Hsu, Chin-Hung Chen, Chia-Jung Hsu, Ssu-I Fu, Yu-Hsiang Lin
  • Patent number: 11682724
    Abstract: A high voltage transistor structure including a substrate, a first drift region, a second drift region, a first cap layer, a second cap layer, a gate structure, a first source and drain region, and a second source and drain region is provided. The first and second drift regions are disposed in the substrate. The first and second cap layers are respectively disposed on the first and second drift regions. The gate structure is disposed on the substrate and located over at least a portion of the first drift region and at least a portion of the second drift region. The first and second source and drain regions are respectively disposed in the first and second drift regions and located on two sides of the gate structure. The size of the first drift region and the size of the second drift region are asymmetric.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: June 20, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Ya Chiu, Ssu-I Fu, Chih-Kai Hsu, Chin-Hung Chen, Chia-Jung Hsu, Yu-Hsiang Lin
  • Publication number: 20230172561
    Abstract: A monitoring device for physiological signal monitoring includes a first light receiving and transmitting device and a control device. The first light receiving and transmitting device generates a first light signal to an object and receives a second light signal to generate a first electrical signal. The control device controls the first light receiving and transmitting device to generate the first light signal in a first period, and controls the first light receiving and transmitting device to receive the second light signal to generate the first electrical signal in a second period. The invention further includes an operating method for physiological signal monitoring.
    Type: Application
    Filed: March 7, 2022
    Publication date: June 8, 2023
    Applicant: Industrial Technology Research Institute
    Inventors: Hsuan-Chi WENG, Chin-Hung WANG, Wei LI, Chia-Chung LIU
  • Publication number: 20230171929
    Abstract: The present disclosure is related to a vapor chamber lid. The vapor chamber lid includes a base plate and a top plate. The base plate includes a plate body, a frame, a plurality of supporting pillars and a chip accommodating portion. The frame surrounds the plate body to define a cooling space. The cooling space is configured to accommodate a working fluid. The supporting pillars are located in the cooling space. The chip accommodating portion is located on the plate body of the base plate and is facing away from the cooling space. The top plate is located on the frame of the base plate to seal the cooling space. An external sidewall of the frame of the base plate is coplanar with an external sidewall of the top plate.
    Type: Application
    Filed: October 11, 2022
    Publication date: June 1, 2023
    Inventors: Chun-Ta YEH, Chin-Hung KUO, Po-Li WANG
  • Publication number: 20230170261
    Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, a metal gate adjacent to the isolation structure, a shallow trench isolation (STI around the fin-shaped structure, and a second isolation structure on the STI. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.
    Type: Application
    Filed: February 1, 2023
    Publication date: June 1, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chi-Ting Wu, Chin-Hung Chen, Yu-Hsiang Lin
  • Publication number: 20230154931
    Abstract: An electronic device may include a display having an array of display pixels on a substrate. The display pixels may be organic light-emitting diode display pixels or display pixels in a liquid crystal display. In an organic light-emitting diode display, hybrid thin-film transistor structures may be formed that include semiconducting oxide thin-film transistors, silicon thin-film transistors, and capacitor structures. The capacitor structures may overlap the semiconducting oxide thin-film transistors. Organic light-emitting diode display pixels may have combinations of oxide and silicon transistors. In a liquid crystal display, display driver circuitry may include silicon thin-film transistor circuitry and display pixels may be based on oxide thin-film transistors. A single layer or two different layers of gate metal may be used in forming silicon transistor gates and oxide transistor gates. A silicon transistor may have a gate that overlaps a floating gate structure.
    Type: Application
    Filed: January 18, 2023
    Publication date: May 18, 2023
    Inventors: Hiroshi Osawa, Kyung-Wook Kim, Ming-Chin Hung, Shih Chang Chang, Yu-Cheng Chen
  • Publication number: 20230155826
    Abstract: A device which can be implemented on a single packaged integrated circuit or a multichip module comprises a plurality of non-volatile memory cells, and logic to use a physical unclonable function to produce a key and to store the key in a set of non-volatile memory cells in the plurality of non-volatile memory cells. The physical unclonable function can use entropy derived from non-volatile memory cells in the plurality of non-volatile memory cells to produce a key. Logic is described to disable changes to data in the set of non-volatile memory cells, and thereby freeze the key after it is stored in the set.
    Type: Application
    Filed: January 17, 2023
    Publication date: May 18, 2023
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chun-Hsiung HUNG, Chin-Hung CHANG
  • Publication number: 20230153255
    Abstract: A method of data synchronization is to be implemented by a redundant server system including an active input/output module (IOM) and a passive IOM. The method includes: allocating a primary transfer buffer in the active IOM; allocating a secondary transfer buffer in the passive IOM; collecting pieces of secondary dedicated-sensor data, and storing the pieces of secondary dedicated-sensor data in the primary transfer buffer at once; collecting pieces of primary dedicated-sensor data; after the pieces of primary dedicated-sensor data have been collected, updating the primary state data based on the pieces of primary dedicated-sensor data thus collected and the pieces of secondary dedicated-sensor data stored in the primary transfer buffer at once, and storing the primary state data thus updated in the secondary transfer buffer; and updating the secondary state data based on the primary state data that have been updated and that are stored in the secondary transfer buffer.
    Type: Application
    Filed: November 3, 2022
    Publication date: May 18, 2023
    Applicant: Mitac Computing Technology Corporation
    Inventors: Chin-Hung TAN, Heng-Chia HSU, Chien-Chung WANG, Yu-Shu YEH, Chen-Yin LIN
  • Publication number: 20230144588
    Abstract: A ventilator mask and a joint thereof are provided. The ventilator mask includes a ventilator mask body and the joint. The joint includes a joint body, an upper cover, and a perforated cover. The joint body includes a first end portion, a second end portion, and a third end portion. The first end portion is configured to be movably connected to the ventilator mask body. The third end portion is configured to communicate with an oxygen source. An opening is disposed between the first and second end portions. The upper cover is pivotally connected to the joint body for closing or opening the opening. The perforated cover is disposed on the second end portion. The perforated cover has a through hole for insertion of a tube. The ventilator mask can be airtightly fitted to the patient’s face. There is no need to remove the ventilator mask for performing sputum suction.
    Type: Application
    Filed: October 31, 2022
    Publication date: May 11, 2023
    Inventors: YI-FONG JHUO, MEI-CHIN HUNG, HSING-LONG LIN, ZU-CHUN LIN, CHIA-JUNG CHEN
  • Patent number: 11646349
    Abstract: A structure of semiconductor device is provided, including a substrate. First and second trench isolations are disposed in the substrate. A height of a portion of the substrate is between a top and a bottom of the first and second trench isolations. A gate insulation layer is disposed on the portion of the substrate between the first and second trench isolations. A first germanium (Ge) doped layer region is disposed in the portion of the substrate just under the gate insulation layer. A second Ge doped layer region is in the portion of the substrate, overlapping with the first Ge doped layer region to form a Ge gradient from high to low along a depth direction under the gate insulation layer. A fluorine (F) doped layer region is in the portion of the substrate, lower than and overlapping with the first germanium doped layer region.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: May 9, 2023
    Assignee: United Microelectronics Corp.
    Inventors: Chia-Jung Hsu, Chin-Hung Chen, Chun-Ya Chiu, Chih-Kai Hsu, Ssu-I Fu, Tsai-Yu Wen, Shi You Liu, Yu-Hsiang Lin
  • Patent number: 11646485
    Abstract: A method for manufacturing a liquid-crystal antenna device is provided. The method includes step (a) providing a first mother substrate. The first mother substrate includes a first region and a second region. The first region has a plurality of first sides. An extension line of at least one of the first sides divides the second region into a first part and a second part. The method also includes the following steps: (b) forming a first electrode layer on the first region and the second region, and (c) cutting the first mother substrate along the first sides of the first region.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: May 9, 2023
    Assignee: INNOLUX CORPORATION
    Inventors: Yi-Hung Lin, Chin-Lung Ting, Hui-Min Huang, Tang-Chin Hung
  • Patent number: 11632273
    Abstract: This disclosure provides methods, devices and systems for determining unavailable spatial streams in uplink multiuser (MU) multiple-in multiple-out (MIMO) communication. In one example, a device transmits, to wireless stations including a first wireless station, a trigger frame configured to elicit a joint transmission, to the device, of a MU packet over spatial streams respectively associated with the wireless stations. The device receives the MU packet over the spatial streams, where each spatial stream of the spatial streams is received by receive chains of the device. The device performs a channel estimation associated with each spatial stream of the spatial streams using each receive chain of the receive chains. The device determines that at least one spatial stream associated with the first wireless station is unavailable based on the channel estimation. The device processes the MU packet from the plurality of spatial streams without the at least one spatial stream.
    Type: Grant
    Filed: December 2, 2021
    Date of Patent: April 18, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Meriam Rezk, Deniz Rende, Kapil Rai, Chin-Hung Chen