Abstract: Provided is a semiconductor device, including a substrate including a pixel region, a gate structure on the substrate in the pixel region, wherein the gate structure comprises a gate dielectric layer and a gate conductive layer on the gate dielectric layer; a dielectric layer located over the substrate and the gate structure; and a contact located in the dielectric layer and electrically connected to the gate conductive layer. The contact includes a doped polysilicon layer in contact with the gate conductive layer; a metal layer located on the doped polysilicon layer, wherein a part of the metal layer is embedded in the doped polysilicon layer; a barrier layer located between the metal layer and the doped polysilicon layer; and a metal silicide layer located between the barrier layer and the doped polysilicon layer.

Abstract: An electronic device is provided. The electronic device includes a working region and a non-working region adjacent to the working region. The electronic device includes a first substrate, a first photo spacer, a second photo spacer, and a plurality of third photo spacers. The first photo spacer is disposed on the first substrate in the working region and has a first thickness. The second photo spacer is disposed on the first substrate in the non-working region and has a second thickness. The plurality of third photo spacers are disposed on the first substrate. The first photo spacer is disposed between two of the plurality of third photo spacers. At least one of the plurality of third photo spacers has a third thickness. The first thickness is different from the second thickness, and the third thickness is less than the first thickness.

Abstract: A centrifugal fan is disclosed and includes a housing, a fan wheel, a first throat portion and a second throat portion. The housing includes a lower cover connected to an upper cover through a peripheral wall to form an accommodation space and an outlet. The upper cover includes an inlet communicated with the outlet. The fan wheel is disposed on the lower cover and accommodated in the accommodation space. The fan wheel is rotated along a rotation direction. The first throat portion is disposed adjacent to a lateral end of the outlet and protrudes from the peripheral wall toward the accommodation space. The second throat portion is disposed adjacent to another lateral end of the outlet, and protrudes from the peripheral wall toward the accommodation space. When the fan wheel is rotated along the rotational direction, an airflow is guided from the first throat portion to the second throat portion.

Abstract: A key structure is provided. The key structure includes a base plate, a key cap and a lifting mechanism is provided. The base plate includes a first bottom wall. The key cap is disposed opposite to the base plate and includes a first cap wall. The lifting mechanism is movably connected between the key cap and the base plate, so that the key cap could reciprocate with respect to the base plate. The lifting mechanism includes a first lower shaft portion and a first upper shaft portion, which are respectively movably connected on the same side of the key cap and the base plate. When the key cap is in a released state, the first upper shaft portion presses against the first cap wall, but the first lower shaft portion is separated from the bottom wall by a maintaining gap.

Abstract: A device which can be implemented on a single packaged integrated circuit or a multichip module comprises a plurality of non-volatile memory cells, and logic to use a physical unclonable function to produce a key and to store the key in a set of non-volatile memory cells in the plurality of non-volatile memory cells. The physical unclonable function can use entropy derived from non-volatile memory cells in the plurality of non-volatile memory cells to produce a key. Logic is described to disable changes to data in the set of non-volatile memory cells, and thereby freeze the key after it is stored in the set.

Abstract: A keyswitch includes a base plate, a keycap, a balance bar, at least one buffer layer, and a membrane switch layer disposed on a base plate. A linking portion of the base plate protruding upward penetrates through the membrane switch layer such that a contact portion of the membrane switch layer is located proximate to the linking portion. A connecting section of the balance bar passes through a through hole of the linking portion. The at least one buffer layer is formed on a lower surface of the contact portion, and extends along a first lateral path and a second lateral path. The contact portion supports the connecting section to abut against a top wall of the linking portion. When the keycap moves upward and downwards, the connecting section pivotally slides on the contact portion, between the first lateral path and the second lateral path.

Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, and a metal gate adjacent to the isolation structure. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.

Abstract: A high voltage transistor structure including a substrate, a first isolation structure, a second isolation structure, a gate structure, a first source and drain region, and a second source and drain region is provided. The first isolation structure and the second isolation structure are disposed in the substrate. The gate structure is disposed on the substrate, at least a portion of the first isolation structure, and at least a portion of the second isolation structure. The first source and drain region and the second source and drain region are located in the substrate on two sides of the first isolation structure and the second isolation structure. The depth of the first isolation structure is greater than the depth of the second isolation structure.

Abstract: A high voltage transistor structure including a substrate, a first drift region, a second drift region, a first cap layer, a second cap layer, a gate structure, a first source and drain region, and a second source and drain region is provided. The first and second drift regions are disposed in the substrate. The first and second cap layers are respectively disposed on the first and second drift regions. The gate structure is disposed on the substrate and located over at least a portion of the first drift region and at least a portion of the second drift region. The first and second source and drain regions are respectively disposed in the first and second drift regions and located on two sides of the gate structure. The size of the first drift region and the size of the second drift region are asymmetric.

Abstract: A method for fabricating of semiconductor device is provided, including providing a substrate. A first trench isolation and a second trench isolation are formed in the substrate. A portion of the substrate is etched to have a height between a top and a bottom of the first and second trench isolations. A germanium (Ge) doped layer region is formed in the portion of the substrate. A fluorine (F) doped layer region is formed in the portion of the substrate, lower than and overlapping with the germanium doped layer region. An oxidation process is performed on the portion of the substrate to form a gate oxide layer between the first and second trench isolations.

Abstract: A boot method for an embedded system is provided. The embedded system includes two mainboards each provided with a baseboard management controller (BMC), a non-volatile memory unit and a network adapter. When the embedded system is turned on, each of the BMCs performs a boot procedure, and then loads an operating system (OS) image file from a corresponding non-volatile memory unit to execute an operating system. When one BMC fails to load the OS image file or to execute the operating system, the BMC causes the corresponding network adapter to communicate with the other network adapter to acquire the OS image file from, the non-volatile memory unit on the other mainboard, so as to replace the OS image file in the corresponding non-volatile memory unit, and directly loads the OS image thus acquired to execute the operating system.

Abstract: According to examples, an apparatus may include a base plate to be coupled to an electronic device, a first movable plate, and a second movable plate. The base plate may include a first edge that may extend in a first direction and a second edge that may extend from the first edge in a second direction that is different than the first direction. The first edge may be disposed adjacent to the second edge. The first movable plate may be rotatably coupled to the first edge of the base plate to selectively support the electronic device in a first orientation. The second movable plate may be rotatably coupled to the second edge of the base plate to selectively support the electronic device in a second orientation.

Abstract: An electronic modulating device is provided. The electronic modulating device includes a first substrate. The first substrate includes a first portion and a second portion. The electronic modulating device also includes a second substrate disposed opposite to the first substrate. The electronic modulating device further includes at least one working device disposed between the first substrate and the second substrate, wherein the working device overlaps the first portion and does not overlap the second portion. In addition, the electronic modulating device includes a first adjustment unit disposed between the first portion of the first substrate and the second substrate. The first adjustment unit has a first elastic coefficient. The electronic modulating device also includes second adjustment unit disposed between the second portion of the first substrate and the second substrate. The second adjustment unit has a second elastic coefficient that is greater than the first elastic coefficient.

Abstract: A memory chip comprises a first memory controller, a first data storage zone, a security unit and an address configuration unit. The first data storage zone is coupled to the first memory controller, and represented by a first physical address range. The security unit is coupled to the first memory controller. The address configuration unit is coupled to the first memory controller. The memory chip is configured to be coupled between a host controller and another memory chip. The another memory chip comprises a second data storage zone represented by a second physical address range. The address configuration unit records one or more relationships of a logical address range corresponding to the first physical address range and the second physical address range. The security unit is configured to encrypt and decrypt data in the first data storage zone and the second data storage zone.

Abstract: In an example, an electronic device may include a housing and a display panel disposed in the housing. Further, the electronic device may include an input assembly disposed in the housing abutting a side of the display panel. The input assembly may include a printed circuit board (PCB), a sensor disposed on the PCB, and a first keep-out zone defined on the PCB on a side of the sensor. Further, the electronic device may include an antenna disposed in the first keep-out zone of the PCB.

Abstract: In one example in accordance with the present disclosure, an electronic device is described. An example electronic device includes an antenna. The example antenna includes a feed point and a first radiator coupled to the feed point. The example antenna also includes a switch coupled to the first radiator and a second radiator coupled to the switch. The example switch (1) disconnects the first radiator from the second radiator when the electronic device is in a first mode; and (2) connects the first radiator to the second radiator when the electronic device is in a second mode.

Abstract: An electronic device may include a housing, an antenna radiator disposed within the housing, a transceiver to connect to the antenna radiator, and a magnet disposed on the antenna radiator. When the magnet is aligned with a magnetic element of an input pen, the magnet may cause the antenna radiator to move proximate to a metal structure of the input pen such that the metal structure and the antenna radiator form an extended antenna.

Abstract: A fluid dispensing scrubber includes a shaft having a first end and a second end; a fluid inlet configured to receive a first fluid from an external source; a reservoir configured to store a second fluid; a valve assembly configured to selectively mix the first fluid and the second fluid; a scrubbing head supported adjacent the first end of the shaft, the scrubbing head including a brush and a motor operable to rotate the brush; a battery pack supported adjacent the second end, the battery pack operable to provide power to the motor; and a dispensing nozzle configured to selectively dispense one or both of the first fluid and the second fluid, the nozzle supported on an exterior surface of the scrubbing head.

Abstract: A transmitter including two radio transceivers and a controller is provided. The first radio transceiver supports a first number of Spatial Streams (SS) for a first Transmission (Tx) opportunity of wireless transmission to a receiver. The second radio transceiver supports a second number of SS for a second Tx opportunity of wireless transmission to the receiver. The first Tx opportunity starts earlier than the second Tx opportunity. The controller determines whether the power consumption of SS utilization in the first and second Tx opportunities exceeds a threshold, and if so, performs one of the following: deferring the second Tx opportunity until the first Tx opportunity ends; and aborting the first Tx opportunity when the second Tx opportunity starts.

Abstract: A control method for charging time sharing in a display apparatus, which includes receiving image data including a plurality of pixel data signals corresponding to a plurality of display driving periods, each display driving period associated with pixel data signals of a respective row of the display apparatus, calculating a plurality of gray variations corresponding to the plurality of display driving periods according to the plurality of pixel data signals, adjusting the plurality of display driving periods to generate a plurality of adjusted display driving periods according to the plurality of gray variations, and generating a gate clock signal according to the plurality of adjusted display driving periods.