Abstract: In some embodiments, the present disclosure relates to a semiconductor device comprising a source and drain region arranged within a substrate. A conductive gate is disposed over a doped region of the substrate. A gate dielectric layer is disposed between the source region and the drain region and separates the conductive gate from the doped region. A bottommost surface of the gate dielectric layer is below a topmost surface of the substrate. First and second sidewall spacers are arranged along first and second sides of the conductive gate, respectively. An inner portion of the first sidewall spacer and an inner portion of the second sidewall spacer respectively cover a first and second top surface of the gate dielectric layer. A drain extension region and a source extension region respectively separate the drain region and the source region from the gate dielectric layer.

Abstract: Disclosed herein are electronic devices that include arrays of dual function light transmit and receive pixels. The pixels of such arrays include a photodetector (PD) structure and a vertical-cavity, surface-emitting laser (VCSEL) diode, both formed in a common stack of epitaxial semiconductor layers. The pixels of the array may be configured by a controller or processor to function either as a light emitter by biasing the VCSEL diode, or as a light detector or receiver by a different bias applied to the PD structure, and this functionality may be altered in time. The array of dual function pixels may be positioned interior to an optical display of an electronic device, in some cases to provide depth sensing or autofocus. The array of pixels may be registered with a camera of an electronic device, such as to provide depth sensing or autofocus.

Abstract: In some implementations, a method of synchronizing a content generation and delivery architecture to reduce the latency associated with image passthrough. The method includes: determining a temporal offset associated with the content generation and delivery architecture to reduce a photon-to-photon latency across the content generation and delivery architecture; obtaining a first reference rate associated with a portion of the content generation and delivery architecture; generating, via synchronization circuitry, a synchronization signal for the content generation and delivery architecture based at least in part on the first reference rate; and operating the content generation and delivery architecture according to the synchronization signal and the temporal offset.

Abstract: A device may include a display that display an image frame that is divided into adjustable regions having respective resolutions based on compensated image data. The device may also include image processing circuitry to generate the compensated image data by applying gains that compensate for burn-in related aging of pixels of the display. The gains are based on an aggregation of history updates indicative of estimated amounts of aging associated with pixel utilization. The circuitry may generate a history update by obtaining boundary data indicative of the boundaries between the adjustable regions, determining an estimated amount of aging, and dynamically resampling the estimated amount of aging by resampling a portion of the estimated amount of aging corresponding to an adjustable region by a factor and resampling of a different portion of the estimated amount of aging corresponding to another adjustable region by a different factor based on the boundary data.

Abstract: A defect-reducing coating method is disclosed, which is characterized by making the coating surface of a sample face the bottom of the coating chamber, so that the sticking particles on side walls of the coating chamber will not fall on the coating surface of the sample during the coating process, thereby a smooth coating layer can be formed on the coating surface of the sample after the coating process is finished.

Abstract: A device may include a display for displaying an image frame based on warped image data and image processing circuitry to generate the warped image data by warping input image data to account for one or more distortions associated with displaying the image. The image processing circuitry may include a two-stage cache architecture having an first cache and an second cache and warp the input image data by generating mapping data indicative of a warp between the input image space and the output image space and fetching the input image data to populate the first cache. Warping may also include populating the second cache with a grouping of pixel values from the first cache that are selected according to a sliding window that traverses the first cache based on the mapping data and interpolating between pixel values of the grouping to generate pixel values of the warped image data.

Abstract: A curved prism array applied to an infrared sensor wherein: the infrared sensor comprises at least an infrared sensing element which is used in detecting infrared signals within a solid-angled FOV and installed inside the curved prism array; the curved prism array has an incident focal plane and a plurality of emergent focal planes, both of which are not parallel with each other, such that infrared signals beyond the solid-angled FOV are received by the incident focal plane, refracted through one of the emergent focal planes and guided toward the infrared sensing element for expansion of the solid-angled FOV of the infrared sensing element.

Abstract: The present disclosure provides an inductance detection method includes steps of: (a) acquiring a stator resistance of the reluctance motor; (b) injecting a high-frequency sinusoidal signal in the d-axis or q-axis direction; (c) injecting an align signal command in the q-axis or d-axis direction; (d) receiving a dq-axes signal generated through injecting the high-frequency sinusoidal signal and the align signal command; (e) sampling a motor feedback signal generated through receiving the dq-axes signal; (f) in the direction of injecting the high-frequency sinusoidal signal, calculating an amplitude difference between the high-frequency sinusoidal signal and the motor feedback signal, and adjusting an amplitude of the high-frequency sinusoidal signal according to the amplitude difference for regulating a feedback amplitude of the motor feedback signal; and (g) when the feedback amplitude reaching an expected amplitude, calculating an apparent inductance of the reluctance motor based on the dq-axes signal, the

Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes a substrate and an interconnect structure. The interconnect structure includes a first conductive feature disposed within a first inter-level dielectric layer. A blocking layer is selectively formed on the first conductive feature without forming the blocking layer on the first inter-level dielectric layer. An alignment feature is selectively formed on the first inter-level dielectric layer without forming the alignment feature on the blocking layer. The blocking layer is removed from the first conductive feature, and a second inter-level dielectric layer is formed on the alignment feature and on the first conductive feature. The second inter-level dielectric layer is patterned to define a recess for a second conductive feature, and the second conductive feature is formed within the recess.

Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.

Abstract: A static auto-tuning system and method for controlling operation of a motor in a system. A speed reference signal is generated resulting in a speed response of the motor. Closed-loop feedback magnifies the rotating friction effect to an observable level. Inertia and rotating friction coefficient values of the system are estimated based on the speed frequency response and a virtual damping coefficient. A fixed low frequency speed signal may result in a first frequency response function for determining virtual damping, and a variable frequency excitation signal may result in a second frequency response function for determining the inertia and rotating friction characteristics. Closed-loop gains are determined based on these characteristics. The excitation signal may be sampled and a peak value in each interval may be identified and stored to produce an envelope of peak values for determining the gain response. Operation of the motor is controlled using the determined gains.

Abstract: A method for forming a chip package structure. The method includes bonding first connectors over a front surface of a semiconductor wafer. The method also includes dicing the semiconductor wafer from a rear surface of the semiconductor wafer to form semiconductor dies and mounting first and second semiconductor dies in the semiconductor dies over a top surface of the interposer substrate. The method further forming an encapsulating layer over the top surface of the interposer substrate to cover the first semiconductor die and the second semiconductor die. A first sidewall of the first semiconductor die faces a second sidewall of the second semiconductor die, and upper portions of the first sidewall and the second sidewall have a tapered contour, to define a top die-to-die distance and a bottom die-to-die distance that is less than the top die-to-die distance.

Abstract: A method and apparatus for automatically generating a meeting summary is disclosed herein. Meeting audio is recorded and converted into a text-based transcript. Handwritten meeting notes are converted into notes text. The transcript and notes text are correlated to provide correlated meeting text. Meeting topics are determined from the correlated meeting text. A meeting summary is generated from the meeting topics.

Abstract: The memory device includes at least one memory block with source and drain sides and a plurality of memory cells arranged in a plurality of word lines. The word lines are arranged in a plurality of independently programmable and erasable sub-blocks. Control circuitry is configured to program the memory cells of a selected sub-block and determine a location of the within the at least one memory block and determine a programming condition of at least one unselected sub-block. The control circuitry is also configured to program at least one word line in the selected sub-block in a plurality of program loops that include pre-charging processes. The control circuitry pre-charges a plurality of channels from either the source or drain side based on at least one of the location of the selected sub-block within the memory block and the programming condition of the at least one unselected sub-block.

Abstract: A method for manufacturing a semiconductor structure includes forming a first interconnect feature in a first dielectric feature, the first interconnect feature including a first conductive element exposed from the first dielectric feature; forming a first cap feature over the first conductive element, the first cap feature including a first cap element which includes a two-dimensional material; forming a second dielectric feature with a first opening that exposes the first cap element; forming a barrier layer over the second dielectric feature while exposing the first cap element from the barrier layer; removing a portion of the first cap element exposed from the barrier layer; and forming a second conductive element in the first opening.

Abstract: The present invention provides a display panel, including a backplane having flexibility, a first fixing member, a front frame having flexibility, and a display module provided between the backplane and the front frame. The backplane has a base plate with a first side. The first fixing member extends corresponding to the first side and has a first predetermined curvature. The first fixing member at least has a first wall body standing upright relative to the base plate, and the first fixing member is relatively fixed to the backplane, so that the curvature of the backplane can be adjusted corresponding to the first fixing member. The front frame is provided in a manner that extends correspondingly to the periphery of the backplane, and is relatively fixed to the backplane, so that the curvature of the front frame is relatively adapted to that of the backplane.

Abstract: A centrifugal heat dissipation fan including a housing and an impeller disposed in the housing on an axis is provided. The housing has at least one inlet on the axis and has a plurality of outlets in different radial directions. A heat dissipation system of an electronic device is also provided.

Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.

Abstract: A compensation system includes a processor configured to determine compensated data for display on a sub-pixel of the display device. The processor may receive image data configured to be displayed on the sub-pixel, convert the gray level data to first voltage data; fetch, from a memory, compressed 1×1 sub-pixel uniformity compensation data for the sub-pixel, and decompress the compressed 1×1 sub-pixel uniformity compensation data via a decompressor. The decompressed data comprises the 1×1 sub-pixel uniformity compensation data for the sub-pixel. The processor may also determine a voltage compensation offset value associated with the sub-pixel based on the second voltage data, generate compensated voltage data based in part on the voltage compensation offset value and the first voltage data, convert the compensated voltage data to compensated gray level data; and transmit the compensated gray level data to pixel driving circuitry associated with the sub-pixel.

Abstract: Provided is an electronic package structure, including a substrate, a first electronic component disposed on the substrate, at least one second electronic component disposed on the substrate, an insulating film disposed on the second electronic component and the substrate, an insulating glue filled onto the second electronic component and the substrate to cover at least part of the insulating film, a liquid metal disposed on the first electronic component, and a heat-dissipating plate disposed on the first electronic component to squeeze the liquid metal. The insulating film and the insulating glue prevent the overflowing liquid metal from contacting the second electronic component and the substrate.