Patents by Inventor Chin-To Chen

Chin-To Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240088095
    Abstract: A method for forming a chip package structure. The method includes bonding first connectors over a front surface of a semiconductor wafer. The method also includes dicing the semiconductor wafer from a rear surface of the semiconductor wafer to form semiconductor dies and mounting first and second semiconductor dies in the semiconductor dies over a top surface of the interposer substrate. The method further forming an encapsulating layer over the top surface of the interposer substrate to cover the first semiconductor die and the second semiconductor die. A first sidewall of the first semiconductor die faces a second sidewall of the second semiconductor die, and upper portions of the first sidewall and the second sidewall have a tapered contour, to define a top die-to-die distance and a bottom die-to-die distance that is less than the top die-to-die distance.
    Type: Application
    Filed: November 24, 2023
    Publication date: March 14, 2024
    Inventors: Chin-Hua WANG, Shin-Puu JENG, Po-Yao LIN, Po-Chen LAI, Shu-Shen YEH, Ming-Chih YEW, Yu-Sheng LIN
  • Patent number: 11929074
    Abstract: A method and apparatus for automatically generating a meeting summary is disclosed herein. Meeting audio is recorded and converted into a text-based transcript. Handwritten meeting notes are converted into notes text. The transcript and notes text are correlated to provide correlated meeting text. Meeting topics are determined from the correlated meeting text. A meeting summary is generated from the meeting topics.
    Type: Grant
    Filed: February 11, 2021
    Date of Patent: March 12, 2024
    Assignee: Dell Products L.P.
    Inventors: Benedict Tiong Chee Tay, Mark John Law, Chin Leong Ong, Jonathan Sebastian Yarborough Wood, Li Weixian, Yunguo Chen
  • Publication number: 20240079062
    Abstract: The memory device includes at least one memory block with source and drain sides and a plurality of memory cells arranged in a plurality of word lines. The word lines are arranged in a plurality of independently programmable and erasable sub-blocks. Control circuitry is configured to program the memory cells of a selected sub-block and determine a location of the within the at least one memory block and determine a programming condition of at least one unselected sub-block. The control circuitry is also configured to program at least one word line in the selected sub-block in a plurality of program loops that include pre-charging processes. The control circuitry pre-charges a plurality of channels from either the source or drain side based on at least one of the location of the selected sub-block within the memory block and the programming condition of the at least one unselected sub-block.
    Type: Application
    Filed: September 6, 2022
    Publication date: March 7, 2024
    Applicant: SanDisk Technologies LLC
    Inventors: Jiacen Guo, Han-Ping Chen, Henry Chin, Guirong Liang, Xiang Yang
  • Publication number: 20240071263
    Abstract: The present invention provides a display panel, including a backplane having flexibility, a first fixing member, a front frame having flexibility, and a display module provided between the backplane and the front frame. The backplane has a base plate with a first side. The first fixing member extends corresponding to the first side and has a first predetermined curvature. The first fixing member at least has a first wall body standing upright relative to the base plate, and the first fixing member is relatively fixed to the backplane, so that the curvature of the backplane can be adjusted corresponding to the first fixing member. The front frame is provided in a manner that extends correspondingly to the periphery of the backplane, and is relatively fixed to the backplane, so that the curvature of the front frame is relatively adapted to that of the backplane.
    Type: Application
    Filed: August 28, 2023
    Publication date: February 29, 2024
    Inventors: MING-CHIN TSAI, CHIA-HSIN JOW, CHI-CHANG CHEN, CHIA-HSIN CHANG
  • Publication number: 20240071822
    Abstract: A method for manufacturing a semiconductor structure includes forming a first interconnect feature in a first dielectric feature, the first interconnect feature including a first conductive element exposed from the first dielectric feature; forming a first cap feature over the first conductive element, the first cap feature including a first cap element which includes a two-dimensional material; forming a second dielectric feature with a first opening that exposes the first cap element; forming a barrier layer over the second dielectric feature while exposing the first cap element from the barrier layer; removing a portion of the first cap element exposed from the barrier layer; and forming a second conductive element in the first opening.
    Type: Application
    Filed: August 31, 2022
    Publication date: February 29, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Lung CHUNG, Shin-Yi YANG, Yu-Chen CHAN, Han-Tang HUNG, Shu-Wei LI, Ming-Han LEE
  • Patent number: 11913472
    Abstract: A centrifugal heat dissipation fan including a housing and an impeller disposed in the housing on an axis is provided. The housing has at least one inlet on the axis and has a plurality of outlets in different radial directions. A heat dissipation system of an electronic device is also provided.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: February 27, 2024
    Assignee: Acer Incorporated
    Inventors: Tsung-Ting Chen, Wen-Neng Liao, Cheng-Wen Hsieh, Yu-Ming Lin, Wei-Chin Chen, Chun-Chieh Wang, Shu-Hao Kuo
  • Patent number: 11916146
    Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chiang Wu, Po-Cheng Chen, Kuo-Chan Huang, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen
  • Patent number: 11908376
    Abstract: A compensation system includes a processor configured to determine compensated data for display on a sub-pixel of the display device. The processor may receive image data configured to be displayed on the sub-pixel, convert the gray level data to first voltage data; fetch, from a memory, compressed 1×1 sub-pixel uniformity compensation data for the sub-pixel, and decompress the compressed 1×1 sub-pixel uniformity compensation data via a decompressor. The decompressed data comprises the 1×1 sub-pixel uniformity compensation data for the sub-pixel. The processor may also determine a voltage compensation offset value associated with the sub-pixel based on the second voltage data, generate compensated voltage data based in part on the voltage compensation offset value and the first voltage data, convert the compensated voltage data to compensated gray level data; and transmit the compensated gray level data to pixel driving circuitry associated with the sub-pixel.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: February 20, 2024
    Assignee: Apple Inc.
    Inventors: Lingtao Wang, Giovanni Carbone, Chaohao Wang, Enkhamgalan Dorjgotov, Sheng Zhang, Jim C Chou, Shereef Shehata, Yung-Chin Chen
  • Publication number: 20240055417
    Abstract: Provided is an electronic package structure, including a substrate, a first electronic component disposed on the substrate, at least one second electronic component disposed on the substrate, an insulating film disposed on the second electronic component and the substrate, an insulating glue filled onto the second electronic component and the substrate to cover at least part of the insulating film, a liquid metal disposed on the first electronic component, and a heat-dissipating plate disposed on the first electronic component to squeeze the liquid metal. The insulating film and the insulating glue prevent the overflowing liquid metal from contacting the second electronic component and the substrate.
    Type: Application
    Filed: August 10, 2023
    Publication date: February 15, 2024
    Applicant: Acer Incorporated
    Inventors: Yu-Ming Lin, Wen-Neng Liao, Cheng-Wen Hsieh, Kuang-Hua Lin, Wei-Chin Chen
  • Patent number: 11897105
    Abstract: A pair of stamping pliers for stamping and bonding includes a first handle, a second handle and a stamping nail. The first handle and the second handle are staggered, pivotally connected, and rotated with respect to each other, and the first handle has a stamping seat which is a stamping groove and a guide through hole provided for moving the stamping nail axially. The second handle has a linking portion linkable to the stamping nail, so that when the second handle is rotated relative to the first handle, the linking portion can be linked to the stamping nail to move the stamping nail axially in the guide through hole.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: February 13, 2024
    Inventor: Chin-Chen Huang
  • Publication number: 20240032271
    Abstract: A semiconductor device includes a first insulating layer over a substrate and a contact plug in the first insulating layer and in contact with the surface of the substrate. The semiconductor device further includes a capacitor structure above the contact plug and a second insulating layer on the first insulating layer and covering the capacitor structure. The capacitor structure includes a conductive layer over the first insulating layer. The semiconductor device further includes a capacitor contact over the capacitor structure. The capacitor contact includes a first contact portion and a second contact portion. The first contact portion penetrates through the second insulating layer and is in contact with the conductive layer of the capacitor structure. The second contact portion connects the outer surface of the first contact portion, and surrounds the lower portion of the first contact portion.
    Type: Application
    Filed: July 25, 2022
    Publication date: January 25, 2024
    Inventors: Jiun-Sheng YANG, Yi-Chin CHEN
  • Patent number: 11868162
    Abstract: A method may include receiving, via a processor, a frame of image data, such that the frame of image data may include an active portion and an idle portion. The active portion may include data for presenting one or more images via a first display of a first electronic device. The method may also include receiving a signal from a second electronic device during the idle portion of the frame of image data, such that the second electronic device is separate from the first display. The method may then involve initiating processing of the frame of image data in response to the signal being received from the second electronic device.
    Type: Grant
    Filed: December 16, 2022
    Date of Patent: January 9, 2024
    Assignee: Apple Inc.
    Inventors: Assaf Menachem, Peter F. Holland, Yung-Chin Chen
  • Patent number: 11865670
    Abstract: The present invention discloses a device for removal of wheel rim burr which comprises a main body, plural positioning wheels, an eccentric wheel disposed on the main body, and at least two brush wheels disposed between two corresponding positioning wheels.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: January 9, 2024
    Assignee: Alex Global Technology, Inc.
    Inventor: Wei-Chin Chen
  • Publication number: 20230388468
    Abstract: In one embodiment, a system includes a first device rendering image data, a second device storing the image data, and a display panel that displays the image data stored in the memory. The first device renders multiple frames of the image data, compresses the multiple frames into a single superframe, and transports the single superframe. The second device receives the single superframe, decompresses the single superframe into the multiple frames of image data, and stores the image data on a memory of the second device.
    Type: Application
    Filed: August 8, 2023
    Publication date: November 30, 2023
    Inventors: Yung-Chin Chen, Michael Bekerman, Guy Côté, Aleksandr M. Movshovich, D. Amnon Silverstein, David R. Pope
  • Patent number: 11828800
    Abstract: The present invention discloses a method for preparing a semiconductor sample for failure analysis, which is characterized by using an adhesive layer comprising a non-volatile and non-liquid adhesive material with higher adhesion to the dielectric materials and lower adhesion to the metallic contact materials to selectively remove part of the dielectric materials in a large area with high uniformity, but completely remain the metallic contact materials, and not chemically react with the semiconductor specimens or even damage to the structures of interest to be analyzed, and different adhesive materials can be selected as the adhesive layer to control the adhesion to the dielectric layer, thereby the removed thickness of the dielectric layer can be controlled to provide a semiconductor specimen for failure analysis.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: November 28, 2023
    Assignee: MSSCORPS CO., LTD.
    Inventors: Chi-Lun Liu, Jung-Chin Chen, Shihhsin Chang
  • Publication number: 20230349386
    Abstract: A centrifugal heat dissipation fan including a hub, a frame, and double-layer fan blade sets is provided. The double-layer fan blade sets surround the hub and are arranged along a radial direction at an inner layer and an outer layer. A gap is maintained along the radial direction between the fan blade set located at the inner layer and the fan blade set located at the outer layer. The frame is connected to the hub and the fan blade set located at the outer layer.
    Type: Application
    Filed: April 25, 2023
    Publication date: November 2, 2023
    Applicant: Acer Incorporated
    Inventors: Cheng-Wen Hsieh, Wen-Neng Liao, Kuang-Hua Lin, Wei-Chin Chen, Tsung-Ting Chen
  • Publication number: 20230352574
    Abstract: A semiconductor component is provided in the form of an enhancement mode high-electron-mobility transistor having an n-i-p semiconductor junction epitaxial structure. The semiconductor component includes: a channel layer and a barrier layer formed on the channel layer. A two-dimensional electron gas (2DEG) is formed in the channel layer adjacent to an interface between the channel layer and the barrier layer. A gate electrode is disposed on the barrier layer. A semiconductor junction structure is disposed and sandwiched between the gate electrode and the barrier layer. The semiconductor junction structure includes a first region doped with a first dopant and in direct contact with the gate electrode, a second region doped with a second dopant different from the first dopant, and a third region being unintentionally doped and sandwiched between the first region and the second region. The semiconductor junction structure depletes a portion of the 2DEG thereunder.
    Type: Application
    Filed: April 29, 2022
    Publication date: November 2, 2023
    Inventors: Shang-Ju Tu, Tien Ching Feng, Chia-Cheng Liu, Ming-Chin Chen, Yu-Jen Liu, Chung-Chih Tsai, Tsung-Cheng Chang, Ya-Yu Yang
  • Patent number: 11802580
    Abstract: An aluminum assembly includes at least an aluminum member. Each aluminum member has a first coupling element and a second coupling element extended from two edges of the aluminum member. The first coupling element has a first groove section and a first protrusion. The first groove section has a first fastener and a second fastener. The second coupling element has a second groove section and a second protrusion. The second groove section has a third fastener and a fourth fastener. As such, the first coupling element of a first aluminum member may be detachably coupled to the second coupling element of a second aluminum member, and the second coupling element of the first aluminum member may be coupled to the first coupling element of a third aluminum member. An aluminum assembly of various forms may be constructed in this way.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: October 31, 2023
    Assignee: emoono CO., LTD.
    Inventors: Pai-Chin Chen, Shiue-Chiau Liu, Yuan-Po Hsu
  • Patent number: 11789259
    Abstract: A vision inspection and correction method, which uses an image adjustment software/device to separate the eyes of the inspected person on an independent display screen, and the visual mark seen by the same vision is designed to be misaligned; through the guidance and interaction of the inspector and the inspected person, the inspector can adjust the image operation to zoom in or out, shift, focus, diverge, and rotate, etc., so that the inspected person's binocular images can be clearly distinguished and adjusted. Then, the binocular images are aligned, and the inspector will implant the correction parameters during the image adjustment process into 3D projectors, VR (virtual reality), AR (augmented reality device), MR hybrid reality device and other equipment to adjust the binocular digital image parameters, so users have, or can provide to a lens maker, personalized adjustment for comfortable images of both eyes.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: October 17, 2023
    Assignee: PASSION LIGHT INC.
    Inventors: Jih-Yi Liao, Chung-Ping Chen, Tse-Yao Wang, Shan-Lin Chang, Ming-Cheng Tsai, Chia-Hung Lin, Ter-Chin Chen, Chao Kai Chang
  • Patent number: D1002636
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: October 24, 2023
    Assignee: VicRound Limited Company
    Inventor: Shui-Chin Chen