Abstract: An optical module packaging structure is provided, which includes a circuit board, an electronic component, a lead frame and a light emitting module. The electronic component is disposed on the circuit board. The lead frame is disposed on the electronic component, in which the lead frame has a first connection portion electrically connected to the circuit board. The light emitting module is disposed on the lead frame, in which the light emitting module includes a first connection pad located at a bottom of the light emitting module, and the first connection pad is electrically connected to the circuit board through the first connection portion of the lead frame. A method of manufacturing the aforementioned optical module packaging structure is also provided.

Abstract: An integrated circuit in a transmitter includes a multi-lane interface, N signal generating circuits, a lane selection circuit and a control circuit. The multi-lane interface has N lanes. M of the N signal generating circuits are configured to generate M clock signals respectively. (N-M) of the N signal generating circuits are configured to generate (N-M) data signals respectively. The lane selection circuit is configured to select M of the N lanes as M clock lanes by coupling the M clock signals to the M clock lanes respectively, and couple one of the (N-M) data signals to one of remaining (N-M) lanes, serving as (N-M) data lanes, according to a data select signal. The control circuit is configured to generate a data select signal according to a lane identifier of the one of the (N-M) lanes. The data select signal has a signal value mapping to the lane identifier.

Abstract: A method includes forming a package, which includes forming a plurality of redistribution lines over a carrier, and forming a thermal dissipation block over the carrier. The plurality of redistribution lines and the thermal dissipation block are formed by common processes. The thermal dissipation block has a first metal density, and the plurality of redistribution lines have a second metal density smaller than the first metal density. The method further includes forming a metal post over the carrier, placing a device die directly over the thermal dissipation block, and encapsulating the device die and the metal post in an encapsulant. The package is then de-bonded from the carrier.

Abstract: A method includes illuminating radiation to a resist layer over a substrate to pattern the resist layer. The patterned resist layer is developed by using a positive tone developer. The patterned resist layer is rinsed using a basic aqueous rinse solution. A pH value of the basic aqueous rinse solution is lower than a pH value of the developer, and a rinse temperature of rinsing the patterned resist layer is in a range of about 20° C. to about 40° C.

Abstract: A photoresist composition includes a conjugated resist additive, a photoactive compound, and a polymer resin. The conjugated resist additive is one or more selected from the group consisting of a polyacetylene, a polythiophene, a polyphenylenevinylene, a polyfluorene, a polypryrrole, a polyphenylene, and a polyaniline. The polyacetylene, polythiophene, polyphenylenevinylene, polyfluorene, polypryrrole, the polyphenylene, and polyaniline includes a substituent selected from the group consisting of an alkyl group, an ether group, an ester group, an alkene group, an aromatic group, an anthracene group, an alcohol group, an amine group, a carboxylic acid group, and an amide group. Another photoresist composition includes a polymer resin having a conjugated moiety and a photoactive compound. The conjugated moiety is one or more selected from the group consisting of a polyacetylene, a polythiophene, a polyphenylenevinylene, a polyfluorene, a polypryrrole, a polyphenylene, and a polyaniline.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a resist layer over a material layer, the resist layer includes an inorganic material. The inorganic material includes a plurality of metallic cores and a plurality of first linkers bonded to the metallic cores. The method includes forming a modified layer over the resist layer, and the modified layer includes an auxiliary. The method includes performing an exposure process on the modified layer and the resist layer, and removing a portion of the modified layer and a first portion of the resist layer by a first developer. The first developer includes a ketone-based solvent having a substituted or unsubstituted C6-C7 cyclic ketone, an ester-based solvent having a formula (b), or a combination thereof.

Abstract: Provided is a material composition and method that includes forming a patterned resist layer on a substrate, where the patterned resist layer has a first line width roughness. In various embodiments, the patterned resist layer is coated with a treatment material, where a first portion of the treatment material bonds to surfaces of the patterned resist layer. In some embodiments, a second portion of the treatment material (e.g., not bonded to surfaces of the patterned resist layer) is removed, thereby providing a treated patterned resist layer, where the treated patterned resist layer has a second line width roughness less than the first line width roughness.

Abstract: A grounding member includes a plurality of contact terminals arranged in a row, a first connection strip connected to a first end of each of the contact terminals, and a second connection strip connected to a second end of each of the contact terminals. Each of the contact terminals has an elastic contact part electrically contacting one of a plurality of grounding terminals of a connector. The grounding member is an integral stamped component that interconnects the grounding terminals.

Abstract: A power management circuit includes an inverter circuit and a latch circuit. The inverter circuit is configured to receive a first control signal from an inverter input terminal and generate a second control signal at an inverter output terminal. The first control signal carries power status information of a first supply voltage. The latch circuit has a latch supply terminal, a first latch input terminal and a second latch input terminal. The latch supply terminal is coupled to a second supply voltage becoming ready before the first supply voltage. The first latch input terminal and the second latch input terminal are coupled to the inverter output terminal and the inverter input terminal respectively. The latch circuit is configured to generate a third control signal according to respective signal levels of the first control signal and the second control signal, and accordingly perform power control of an integrated circuit.

Abstract: A connector includes a housing, a row of terminals disposed in the housing, and a grounding member having a flat body extending across the row of terminals. The row of terminals has a pair of signal terminals and a pair of grounding terminals located on opposite sides of the pair of the signal terminals. The flat body at least partially covers the pair of signal terminals. The grounding member has a plurality of grounding arms extending from a plane of the flat body. Each of the grounding arms abuts against one of the grounding terminals.

Abstract: A current transmission assembly and a current transmission system are provided. The current transmission system includes the current transmission assembly and a circuit board structure. The current transmission assembly includes a pluggable component, at least one conductor component, and at least one electrically connecting component. The pluggable component includes a housing, at least one set of electrically conductive arms, and at least one connecting member. The at least one sets of electrically conductive arms is disposed inside the housing. The at least one conductor component includes an electrical insulator and a wire main body. The electrical insulator encircles the wire main body, so that a first terminal and a second terminal are exposed from the wire main body, and the first terminal is connected to the at least one two connecting member.

Abstract: A voltage regulator circuit includes a first amplifier, a second amplifier and a transistor. Respective first input terminals of the first and second amplifiers are coupled to a first reference voltage and a second reference voltage, respectively. A connection terminal of the transistor is coupled to a supply voltage. A control terminal of the transistor is selectively coupled to one of respective output terminals of the first and second amplifiers. When the control terminal of the transistor is coupled to the output terminal of the first amplifier, another connection terminal of the transistor is coupled to a second input terminal of the first amplifier to output a regulated voltage. When the control terminal of the transistor is coupled to the output terminal of the second amplifier, the another connection terminal of the transistor is coupled to a second input terminal of the second amplifier to output the regulated voltage.

Abstract: A phase-locked loop circuit includes a phase frequency detector (PFD) circuit, a digital code generator circuit, a frequency divider and an oscillator circuit. The PFD circuit is configured to detect a difference in phase and frequency between a reference clock and a feedback clock to generate a first control signal and a second control signal. The digital code generator circuit is configured to process the second control signal to generate a digital code. The frequency divider is configured to receive an output clock to generate the feedback clock. The oscillator circuit is configured to generate the output clock according to the first control signal and the digital code. A frequency of the output clock is determined according to a first control parameter and a second control parameter of different types. The first and second control parameters are adjusted in response to the first control signal and the digital code respectively.

Abstract: A voltage regulator circuit includes a first amplifier, a second amplifier and a transistor. Respective first input terminals of the first and second amplifiers are coupled to a first reference voltage and a second reference voltage, respectively. A connection terminal of the transistor is coupled to a supply voltage. A control terminal of the transistor is selectively coupled to one of respective output terminals of the first and second amplifiers. When the control terminal of the transistor is coupled to the output terminal of the first amplifier, another connection terminal of the transistor is coupled to a second input terminal of the first amplifier to output a regulated voltage. When the control terminal of the transistor is coupled to the output terminal of the second amplifier, the another connection terminal of the transistor is coupled to a second input terminal of the second amplifier to output the regulated voltage.

Abstract: An electrical connector includes a housing, first and second rows of terminals arranged in the housing, and a ground shield assembly. The first and second rows of terminals are separated from each other and adapted to electrically connect with corresponding terminals of a mated electrical connector. The first and second rows of terminals each include a ground terminal connected to a ground layer of a circuit board and a signal terminal connected to a signal lead wire of the circuit board. The ground shield assembly is positioned between the signal terminal of the first row of terminals and the signal terminal of the second row of terminals and is electrically connected to the ground layer. The ground shield assembly is in electrical contact with a corresponding ground terminal at at least one position of each of at least one ground terminal of the first and/or second row of terminals.

Abstract: A current transmission assembly and a current transmission system are provided. The current transmission system includes the current transmission assembly and a circuit board structure. The current transmission assembly includes a pluggable component, at least one conductor component, and at least one electrically connecting component. The pluggable component includes a housing, at least one set of electrically conductive arms, and at least one connecting member. The at least one sets of electrically conductive arms is disposed inside the housing. The at least one conductor component includes an electrical insulator and a wire main body. The electrical insulator encircles the wire main body, so that a first terminal and a second terminal are exposed from the wire main body, and the first terminal is connected to the at least one two connecting member.

Abstract: An electrical connector comprises an outer housing, an insulating housing installed on the outer housing, a pair of terminal assemblies, and a shielding member. The terminal assemblies are installed in the insulating housing and are spaced apart from each other in a first direction to define an insertion space therebetween adapted to receive a connection terminal of a mating connector. Each terminal assembly includes a plurality of conductive terminals arranged in rows in a second direction perpendicular to the first direction. The plurality of conductive terminals of each terminal assembly include a signal terminal and a ground terminal. The shielding member is positioned at least partially between the two terminal assemblies in the first direction and includes a contact arm in electrical contact with the ground terminal.

Abstract: A phase-locked loop circuit includes a phase frequency detector (PFD) circuit, a digital code generator circuit, a frequency divider and an oscillator circuit. The PFD circuit is configured to detect a difference in phase and frequency between a reference clock and a feedback clock to generate a first control signal and a second control signal. The digital code generator circuit is configured to process the second control signal to generate a digital code. The frequency divider is configured to receive an output clock to generate the feedback clock. The oscillator circuit is configured to generate the output clock according to the first control signal and the digital code. A frequency of the output clock is determined according to a first control parameter and a second control parameter of different types. The first and second control parameters are adjusted in response to the first control signal and the digital code respectively.

Abstract: A current transmission assembly and a current transmission system are provided. The current transmission system includes the current transmission assembly and a circuit board structure. The current transmission assembly includes a pluggable component, at least one conductor component, and at least one electrically connecting component. The pluggable component includes a housing, two sets of electrically conductive arms, and two connecting members. Each of the two sets of electrically conductive arms is disposed inside the housing. Each of the conductor components includes an electrical insulator and a wire main body. The electrical insulator encircles the wire main body, so that a first terminal and a second terminal are exposed from the wire main body, and the first terminal is connected to one of the two connecting members. Each of the electrically connecting components includes a connecting portion, to which the second terminal of the wire main body is fixed.

Abstract: The invention relates to an expression system for controlling a network in a cell, wherein the network comprises an actuator molecule and an output molecule, wherein the output molecule is positively or negatively regulated by the actuator molecule, wherein the expression system comprises a recombinant gene encoding a first controller molecule, wherein the first controller molecule positively or negatively regulates the actuator molecule. The invention further relates to a cell comprising the expression system, to a cell for use as a medicament and to a method for controlling a network in a cell.