Abstract: A method of forming an oxide layer includes the following steps. A substrate is provided. A surface of the substrate is treated to form an oxygen ion-rich surface. A spin-on-dielectric layer is formed on the oxygen ion-rich surface of the substrate. The present invention also provides a method of forming an oxide layer including the following steps. A substrate is provided. A surface of the substrate is treated with a hydrogen peroxide (H2O2) solution or a surface of the substrate is treated with oxygen containing gas, to form an oxygen ion-rich surface. A spin-on-dielectric layer is formed on the oxygen ion-rich surface of the substrate.

Abstract: The present disclosure provides an apparatus for a semiconductor lithography process in accordance with some embodiments. The apparatus includes a pellicle membrane, a pellicle frame attached to the pellicle membrane. The pellicle frame has a surface that defines at least one groove. The apparatus further includes a substrate that is in contact with the surface of the pellicle frame such that the grove is positioned between the pellicle frame and the substrate.

Abstract: The present invention provides pad arrangements, termination circuits, clock/data recovery circuits, and deserialization architecture for a physical layer circuitry including a four-signal or six-signal physical medium attachment sublayer (PMA).

Abstract: The present invention provides a method for fabricating a semiconductor device, comprising at least the steps of: providing a substrate in which a memory region and a peripheral region are defined, the memory region includes a plurality of memory cells, each memory cell includes at least a first transistor and a capacitor, the peripheral region compress a second transistor, a first insulating layer is formed within the memory region and the peripheral region by an atomic layer deposition process, covering the capacitor of the memory cells in the memory region and the second transistor in the peripheral region, and a second insulating layer is formed, overlying the first insulating layer and the peripheral region. Finally, a contact structure is formed within the second insulating layer, and electrically connecting the second transistor.

Abstract: The present invention provides a method for forming an amorphous silicon multiple layer structure, the method comprises the flowing steps: first, a substrate material layer is provided, next, a first amorphous silicon layer is formed on the substrate material layer, wherein the first amorphous silicon layer includes a plurality of hydrogen atoms disposed therein, afterwards, an UV curing process is performed to the first amorphous silicon layer, so as to remove the hydrogen atoms from the first amorphous silicon layer, finally, a second amorphous silicon layer is formed on the first amorphous silicon layer.

Abstract: A method of forming a bit line gate structure of a dynamic random access memory (DRAM) includes the following. A hard mask layer is formed on a metal stack by a chemical vapor deposition process importing nitrogen (N2) gases and then importing amonia (NH3) gases. The present invention also provides a bit line gate structure of a dynamic random access memory (DRAM) including a metal stack and a hard mask. The metal stack includes a polysilicon layer, a titanium layer, a titanium nitride layer, a first tungsten nitride layer, a tungsten layer and a second tungsten nitride layer stacked from bottom to top. The hard mask is disposed on the metal stack.

Abstract: A transition enforcing coding (TEC) receiver includes a delay line circuit, a transition detection circuit, a data sampling circuit, and a skew calibration circuit. The delay line circuit employs a calibrated delay setting to delay a plurality of vector signals to generate a plurality of delayed vector signals under a normal mode, respectively. The transition detection circuit detects a transition of at least one specific delayed vector signal among the delayed vector signals. The data sampling circuit samples the vector signals according to a sampling timing, wherein the sampling timing is determined based on an output of the transition detection circuit. The skew calibration circuit sets the calibrated delay setting under a calibration mode, wherein transition skew between different delayed vector signals is reduced by the calibrated delay setting under the normal mode.

Abstract: A transition enforcing coding (TEC) receiver includes a first delay line circuit, a transition detection circuit, and a data sampling circuit. The first delay line circuit delays a plurality of vector signals to generate a plurality of delayed vector signals, respectively. The transition detection circuit detects a transition of at least one specific delayed vector signal among the delayed vector signals. The data sampling circuit samples the vector signals according to a sampling timing determined based on an output of the transition detection circuit.

Abstract: The present disclosure provides an apparatus for a semiconductor lithography process in accordance with some embodiments. The apparatus includes a pellicle membrane, a pellicle frame attached to the pellicle membrane. The pellicle frame has a surface that defines at least one groove. The apparatus further includes a substrate that is in contact with the surface of the pellicle frame such that the grove is positioned between the pellicle frame and the substrate.

Abstract: A transition enforcing coding (TEC) receiver includes a delay line circuit, a transition detection circuit, a data sampling circuit, and a skew calibration circuit. The delay line circuit employs a calibrated delay setting to delay a plurality of vector signals to generate a plurality of delayed vector signals under a normal mode, respectively. The transition detection circuit detects a transition of at least one specific delayed vector signal among the delayed vector signals. The data sampling circuit samples the vector signals according to a sampling timing, wherein the sampling timing is determined based on an output of the transition detection circuit. The skew calibration circuit sets the calibrated delay setting under a calibration mode, wherein transition skew between different delayed vector signals is reduced by the calibrated delay setting under the normal mode.

Abstract: A system and method of determining a cell layout are disclosed. The method includes receiving a circuit design corresponding to a predetermined circuit design, the circuit design having a first set of cells and abutting adjacent cells in the first set of cells, the abutted cells having a first boundary pattern therebetween. The first boundary pattern is exchanged with a second boundary pattern based on a number or positions of signal wires in the first boundary pattern. A cell layout for use in a patterning process can then be determined, the cell layout including the second boundary pattern.

Abstract: A transition enforcing coding (TEC) receiver includes a first delay line circuit, a transition detection circuit, and a data sampling circuit. The first delay line circuit delays a plurality of vector signals to generate a plurality of delayed vector signals, respectively. The transition detection circuit detects a transition of at least one specific delayed vector signal among the delayed vector signals. The data sampling circuit samples the vector signals according to a sampling timing determined based on an output of the transition detection circuit.

Abstract: The present disclosure relates to a method and apparatus for forming a multiple patterning lithograph (MPL) compliant integrated circuit layout by operating a construction validation check on unassembled IC cells to enforce design restrictions that prevent MPL conflicts after assembly. In some embodiments, the method is performed by generating a plurality of unassembled integrated circuit (IC) cells having a multiple patterning design layer. A construction validation check is performed on the unassembled IC cells to identify violating IC cells having shapes disposed in patterns comprising potential multiple patterning coloring conflicts. Design shapes within a violating IC cell are adjusted to achieve a plurality of violation free IC cells. The plurality of violation free IC cells are then assembled to form an MPL compliant IC layout. Since the MPL compliant IC layout is free of coloring conflicts, a decomposition algorithm can be operated without performing a post assembly color conflict check.

Abstract: A system and method of determining a cell layout are disclosed. The method includes receiving a circuit design corresponding to a predetermined circuit design, the circuit design having a first set of cells and abutting adjacent cells in the first set of cells, the abutted cells having a first boundary pattern therebetween. The first boundary pattern is exchanged with a second boundary pattern based on a number or positions of signal wires in the first boundary pattern. A cell layout for use in a patterning process can then be determined, the cell layout including the second boundary pattern.

Abstract: A barrier film for blocking moisture and oxygen transmission includes a single layer grown from a precursor of organic silicide by a chemical vapor deposition, having at least silicon (Si) atoms, oxygen (O) atoms and carbon (C) atoms with atomic ratios of C/Si in a range of about 0.1-0.5, and O/Si in a range of about 2.0-2.5. The Si and O atoms form four bonding structures: Si(—O)4, Si(—O)3, Si(—O)2, and Si(—O)1, in the single layer. In the total amount of the four bonding structures being 100%, the bonding structures of Si(—O)4, Si(—O)3, Si(—O)2, and Si(—O)1 are in ranges of about 50%-99.9%, 0.01%-50%, 0%-10%, and 0%-10%, respectively.

Abstract: A screw with double notches includes a head portion, a shank portion extended outward from the head portion, a threaded section spirally surrounded on the shank portion. Wherein, a raw section on the shank portion is provided with a cambered surface formed integral with the shank portion in cross-section, and a notched section relative to the raw section has two cutting notches separately depressed into the shank portion and disposed near an end of the shank portion, thereby forming a protrudent part between the two cutting notches. By means of the cooperation of the cutting notches and the raw section, the cutting capability and the removal of debris are increased so that a fastened object is prevented from split. Thereby, the drilling speed is promoted, and the effort to rotate the screw is lessened. While the supporting strength of the screw is improved, the screw does not break easily while screwing.

Abstract: A versatile fastener including at least two flat areas formed on a cutting part, and an accommodating area disposed between any two of the flat areas. At least two cutting faces are convergent to form the accommodating area, and first and second cutting edges are respectively formed at a connection between each cutting face and flat area. In operation, the flat areas facilitate the first and the second cutting edges to promote a stable balance with the object, thereby allowing the debris to be swiftly guided out of the accommodating areas. Consequently, it is difficult to crack the object while imparting forces thereon, so as to lower the screwing resistance and the fastening torque as well as increase the combining efficiency.

Abstract: A touch sensing apparatus includes at least one sensing key and a processing circuit. Each of the sensing key includes a signal receiving component for receiving a driving signal, a first sensing block and a reference block. The first sensing block is coupled to the signal receiving component, and arranged to generate a first sensing signal according to a touch event and the driving signal. The reference block is coupled to the signal receiving component, and arranged to generate a reference signal according to the touch event and the driving signal. The processing circuit is coupled to the sensing key, and arranged to provide the driving signal and receive the first sensing signal and reference signal, generate a sensing output of the sensing key according to the reference signal and first sensing signal generated by the sensing key, and generate the touch sensing result according to the sensing output.

Abstract: A screw with double notches includes a head portion, a shank portion extended outward from the head portion, a threaded section spirally surrounded on the shank portion. Wherein, a raw section on the shank portion is provided with a cambered surface formed integral with the shank portion in cross-section, and a notched section relative to the raw section has two cutting notches separately depressed into the shank portion and disposed near an end of the shank portion, thereby forming a protrudent part between the two cutting notches. By means of the cooperation of the cutting notches and the raw section, the cutting capability and the removal of debris are increased so that a fastened object is prevented from split. Thereby, the drilling speed is promoted, and the effort to rotate the screw is lessened. While the supporting strength of the screw is improved, the screw does not break easily while screwing.

Abstract: The present invention pertains to a versatile fastener essentially comprising at least two flat areas formed on a cutting part, and an accommodating area disposed between any two of the flat areas. Wherein, at least two cutting faces are convergent to form the accommodating area, a first and a second cutting edges are respectively formed at a connection between each cutting face and flat area. In operation, the flat areas facilitate the first and the second cutting edges to promote a stable balance with the object, thereby allowing the debris to be swiftly guided out of the accommodating areas. Consequently, it is difficult to crack the object while imparting forces thereon so as to lower the screwing resistance and the fastening torque as well as preferably increase the combining efficiency.