Abstract: A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes a first semiconductor die, an insulating encapsulation laterally encapsulating the first semiconductor die, an electromagnetic shielding structure enclosing the first semiconductor die and a first portion of the insulating encapsulation, and a redistribution structure. The electromagnetic shielding structure includes a first conductive layer and a dielectric frame laterally covering the first conductive layer. The first conductive layer surrounds the first portion of the insulating encapsulation and extends to cover a first side of the first semiconductor die. The dielectric frame includes a first surface substantially leveled with the first conductive layer.

Abstract: An electronic device and a manufacturing method thereof are provided. The electronic device includes a chip package, an antenna pattern, and an insulating layer. The chip package includes a semiconductor die and an insulating encapsulation enclosing the semiconductor die. The antenna pattern is electrically coupled to the chip package, where a material of the antenna pattern comprises a conductive powder having fused metal particles. The insulating layer disposed between the chip package and the antenna pattern, where the antenna pattern includes a first surface in contact with the insulating layer, and a second surface opposite to the first surface, and a surface roughness of the second surface is greater than a surface roughness of the first surface.

Abstract: A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, antenna elements and a first insulating film. The insulating encapsulant is encapsulating the at least one semiconductor die, the insulating encapsulant has a first surface and a second surface opposite to the first surface. The first redistribution layer is disposed on the first surface of the insulating encapsulant. The second redistribution layer is disposed on the second surface of the insulating encapsulant. The antenna elements are located over the second redistribution layer. The first insulating film is disposed in between the second redistribution layer and the antenna elements, wherein the first insulating film comprises a resin rich region and a filler rich region, the resin rich region is located in between the filler rich region and the second redistribution layer and separating the filler rich region from the second redistribution layer.

Abstract: Package structures and methods for forming the same are provided. The method includes forming a redistribution structure embedded in a passivation layer over a carrier substrate and bonding an integrated circuit die to the redistribution structure through first connectors. The method further includes removing the carrier substrate to expose a bottom portion of the redistribution structure and removing the bottom portion of the redistribution structure to form an opening in the passivation layer. The method further includes forming a second connector over the redistribution structure. In addition, the second connector includes an extending portion extending into the opening in the passivation layer.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a first semiconductor die, at least one first conductive connector disposed beside the first semiconductor die and electrically coupled to the first semiconductor die, an insulating encapsulation laterally encapsulating the first semiconductor die and the at least one first conductive connector, and a redistribution structure disposed on the insulating encapsulation and being in contact with the first semiconductor die and the at least one first conductive connector. A thickness of the at least one first conductive connector is less than a thickness of the insulating encapsulation.

Abstract: A manufacturing method of integrated fan-out package includes following steps. First and second dies are provided on adhesive layer formed on carrier. Heights of first and second dies are different. First and second dies respectively has first and second conductive posts each having substantially a same height. The dies are pressed against adhesive layer to make active surfaces thereof be in direct contact with adhesive layer and conductive posts thereof be submerged into adhesive layer. Adhesive layer is cured. Encapsulant is formed to encapsulate the dies. Carrier is removed from adhesive layer. Heights of first and second conductive posts are reduced and portions of the adhesive layer is removed. First and second conductive posts are laterally wrapped by and exposed from adhesive layer. Top surfaces of first and second conductive posts are leveled. Redistribution structure is formed over adhesive layer and is electrically connected to first and second conductive posts.

Abstract: A method of forming a package structure includes the following processes. A die is attached to a polymer layer. An encapsulant is formed over the polymer layer to encapsulate sidewalls of the die. A RDL structure is formed on the encapsulant and the die. A conductive terminal is electrically connected to the die through the RDL structure. A light transmitting film is formed on the polymer layer. An alignment process is performed, and the alignment process uses an optical equipment to see through the light transmitting film to capture the alignment information included in the polymer layer. A singulating process is performed to singulate the package structure according to the alignment information.

Abstract: A molding apparatus is configured for molding a semiconductor device and includes a lower mold and an upper mold. The lower mold is configured to carry the semiconductor device. The upper mold is disposed above the lower mold for receiving the semiconductor device and includes a mold part and a dynamic part. The mold part is configured to cover the upper surface of the semiconductor device. The dynamic part is disposed around a device receiving region of the upper mold and configured to move relatively to the mold part. A molding method and a molded semiconductor device are also provided.

Abstract: A package structure including a semiconductor die, a warpage control layer, an insulating encapsulant and a redistribution layer is provided. The semiconductor die has an active surface and a backside surface opposite to the active surface. The warpage control layer is disposed on the backside surface of the semiconductor die, wherein the warpage control layer comprises a material having a Young's Modulus of 100 GPa or more. The insulating encapsulant is encapsulating the semiconductor die and the warpage control layer. The redistribution layer is located on the insulating encapsulant and over the active surface of the semiconductor die.

Abstract: A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A core layer and a dielectric layer are sequentially stacked over the package array. The core layer includes a plurality of cavities. A plurality of first conductive patches is formed on the dielectric layer above the cavities.

Abstract: A semiconductor device including a chip package, a dielectric structure, and a first antenna pattern is provided. The dielectric structure is disposed on the chip package and includes a cavity and a vent in communication with the cavity. The first antenna pattern is disposed on the dielectric structure, wherein the chip package is electrically coupled to the first antenna pattern, and the cavity of the dielectric structure is disposed between the chip package and the first antenna pattern.

Abstract: A device includes a conductive layer including a bottom portion, and a sidewall portion over the bottom portion, wherein the sidewall portion is connected to an end of the bottom portion. An aluminum-containing layer overlaps the bottom portion of the conductive layer, wherein a top surface of the aluminum-containing layer is substantially level with a top edge of the sidewall portion of the conductive layer. An aluminum oxide layer is overlying the aluminum-containing layer. A copper-containing region is over the aluminum oxide layer, and is spaced apart from the aluminum-containing layer by the aluminum oxide layer. The copper-containing region is electrically coupled to the aluminum-containing layer through the top edge of the sidewall portion of the conductive layer.

Abstract: In accordance with some embodiments, a package-on-package (PoP) structure includes a first semiconductor package having a first side and a second side opposing the first side, a second semiconductor package having a first side and a second side opposing the first side, and a plurality of inter-package connector coupled between the first side of the first semiconductor package and the first side of the second semiconductor package. The PoP structure further includes a first molding material on the second side of the first semiconductor package. The second side of the second semiconductor package is substantially free of the first molding material.

Abstract: An embodiment is a method including bonding a first package to a first set of conductive pads of a second package with a first set of solder joints, testing the first package for defects, heating the first set of solder joints by directing a laser beam at a surface of the first package based on testing the first package for defects, after the first set of solder joints are heated, removing the first package, and bonding a third package to the first set of conductive pads of the second package.

Abstract: A method includes performing a first laser shot on a first portion of a top surface of a first package component. The first package component is over a second package component, and a first solder region between the first package component and the second package component is reflowed by the first laser shot. After the first laser shot, a second laser shot is performed on a second portion of the top surface of the first package component. A second solder region between the first package component and the second package component is reflowed by the second laser shot.

Abstract: A package structure includes a semiconductor device, a molding compound, a first dielectric layer, and a through-via. The molding compound is in contact with a sidewall of the semiconductor device. The first dielectric layer is over the molding compound and the semiconductor device. The through-via is in the molding compound and the first dielectric layer. The through-via is a continuous element and in contact with the first dielectric layer.

Abstract: A clamping mechanism is provided to clamp a die set on a carrier of a machine. The clamping mechanism utilizes a first pushing block to push a locating shaft of the die set to allow a top surface of the locating shaft to contact a mounting surface of the carrier and utilizes a second pushing block to push the locating shaft to allow a first contacting surface of the locating shaft to contact a reference surface of a cage base such that the die set will not clamp on the carrier of the machine with shift or skew errors.

Abstract: A method for forming a package structure is provided. The method includes forming a protective layer to surround a semiconductor die and forming a conductive structure over the protective layer. The method also includes disposing a polymer-containing material over the protective layer to partially surround the conductive structure. The method further includes curing the polymer-containing material to form a warpage-control element.

Abstract: In an embodiment, a package structure including an electro-optical circuit board, a fanout package disposed over the electro-optical circuit board is provided. The electro-optical circuit board includes an optical waveguide. The fanout package includes a first optical input/output portion, a second optical input/output portion and a plurality of electrical input/output terminals electrically connected to the electro-optical circuit board. The first optical input/output portion is optically coupled to the second optical input/output portion through the optical waveguide of the electro-optical circuit board.

Abstract: A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A dielectric layer having a core layer formed thereon is provided. The core layer includes a plurality of cavities penetrating through the core layer. The dielectric layer and the core layer are attached onto the package array such that the core layer is located between the dielectric layer and the package array. A plurality of first conductive patches is formed on the dielectric layer above the cavities.