Abstract: A memory structure disclosed in the present invention features a control gate and floating gates being positioned in recessed trenches. A method of fabricating the memory structure includes the steps of first providing a substrate having a first recessed trench. Then, a first gate dielectric layer is formed on the first recessed trench. A first conductive layer is formed on the first gate dielectric layer. After that, the first conductive layer is etched to form a spacer which functions as a floating gate on a sidewall of the first recessed trench. A second recessed trench is formed in a bottom of the first recessed trench. An inter-gate dielectric layer is formed on a surface of the spacer, a sidewall and a bottom of the second recessed trench. A second conductive layer formed to fill up the first and the second recessed trench.

Abstract: A semiconductor component includes a substrate, two isolation structures, a conductor pattern and a dielectric layer. The isolation structures are disposed in the substrate, and each of the isolation structures has protruding portions protruding from the surface of the substrate. A trench is formed between the protruding portions. The included angle formed by the sidewall of the protruding portion and the surface of the substrate is an obtuse angle. The conductor pattern is disposed in the trench and fills the trench up. The dielectric layer is disposed between the conductor pattern and the substrate.

Abstract: A memory structure including a substrate, dielectric patterns, spacer patterns, a first dielectric layer, a conductor pattern, a second dielectric layer and doped regions is described. The dielectric patterns are disposed on the substrate. The spacer patterns are disposed on each sidewall of each of the dielectric patterns respectively. The first dielectric layer is disposed between the spacer patterns and the substrate. The conductor pattern is disposed on the substrate and covers the spacer patterns. The second dielectric layer is disposed between the spacer patterns and the conductor pattern. The doped regions are disposed in the substrate under each of the dielectric patterns respectively.

Abstract: The invention provides a flash memory device and a method for fabricating thereof. The device comprises a gate stack layer of a gate dielectric layer and a gate polysilicon layer formed on a substrate, a stack layer comprising a floating polysilicon layer and gate spacer formed on the sidewall of the gate stack layer. A metal layer is formed on the gate stack layer and is utilized in place of a portion of the gate polysilicon layer. Because the metal layer has relatively high conductivity and is electrically connected to a metal plug later formed, current velocity of the device is increased to improve performance.

Abstract: A memory structure including a substrate, a first dielectric layer, a first conducting layer, a second conducting layer, a second dielectric layer, a spacer and a doped region is provided. The substrate has a trench wherein. The first dielectric layer is disposed on the interior surface of the trench. The first conducting layer is disposed on the first dielectric layer of the lower portion of the trench. The second conducting layer is disposed above the first conducting layer and filling the trench. The second dielectric layer is disposed between the first conducting layer and the second conducting layer. The spacer is disposed between the first dielectric layer and the second conducting layer. The doped region is disposed in the substrate of a side of the trench.

Abstract: A vertical DRAM and fabrication method thereof. The vertical DRAM has a plurality of memory cells on a substrate, and each of the memory cells has a trench capacitor, a vertical transistor, and a source-isolation oxide layer in a deep trench. The main advantage of the present invention is to form an annular source diffusion and an annular drain diffusion of the vertical transistor around the sidewall of the deep trench. As a result, when a gate of the transistor is turned on, an annular gate channel is provided. The width of the gate channel of the present invention is therefore increased.

Abstract: The present invention provides a method of manufacturing a FinFET transistor, comprising the steps of: forming a plurality of trenches in a semiconductor substrate, forming a dielectric layer on the semiconductor substrate and filling the trenches, and etching back the dielectric layer to a level below the surface of the substrate to form one or more semiconductor fins standing between the trenches as an active region, such as a source, drain, and channel for the FinFET transistor.

Abstract: A stacked gate vertical flash memory and a fabrication method thereof. The stacked gate vertical flash memory comprises a semiconductor substrate with a trench, a source conducting layer formed on the bottom of the trench, an insulating layer formed on the source conducting layer, a gate dielectric layer formed on a sidewall of the trench, a conducting spacer covering the gate dielectric layer as a floating gate, an inter-gate dielectric layer covering the conducting spacer, and a control gate conducting layer filled in the trench.

Abstract: The present invention discloses a multi-bit stacked-type non-volatile memory having a spacer-shaped floating gate and a manufacturing method thereof. The manufacturing method includes forming a patterned dielectric layer containing arsenic on a semiconductor substrate, wherein the patterned dielectric layer defines an opening as an active area. A dielectric spacer is formed on a side wall of the patterned dielectric layer and a gate dielectric layer is formed on the semiconductor substrate. A source/drain region is formed by thermal driving method making arsenic diffusion from the patterned dielectric layer into the semiconductor substrate. A spacer-shaped floating gate is formed on the side wall of the dielectric spacer and the gate dielectric layer. An interlayer dielectric layer is formed on the spacer-shaped floating gate. A control gate is formed on the interlayer dielectric layer and fills the opening of the active area.

Abstract: A method for fabricating a vertical nitride read-only memory (NROM) cell. A substrate having at least one trench is provided. A spacer is formed over the sidewall of the trench. Subsequently, ion implantation is performed on the substrate using the spacer as a mask to form doping areas as bit lines in the substrate near its surface and the bottom of the trench. Bit line oxides are formed over each of the doping areas. After the spacer is removed, a conformable insulating layer as gate dielectric is deposited on the sidewall of the trench and the surface of the bit line oxide. Finally, a conductive layer as a word line is deposited over the insulating layer and fills in the trench.

Abstract: The present invention discloses a multi-bit stacked-type non-volatile memory having a spacer-shaped floating gate and a manufacturing method thereof. The manufacturing method includes forming a patterned dielectric layer containing arsenic on a semiconductor substrate, wherein the patterned dielectric layer defines an opening as an active area. A dielectric spacer is formed on a side wall of the patterned dielectric layer and a gate dielectric layer is formed on the semiconductor substrate. A source/drain region is formed by thermal driving method making arsenic diffusion from the patterned dielectric layer into the semiconductor substrate. A spacer-shaped floating gate is formed on the side wall of the dielectric spacer and the gate dielectric layer. An interlayer dielectric layer is formed on the spacer-shaped floating gate. A control gate is formed on the interlayer dielectric layer and fills the opening of the active area.

Abstract: A method for fabricating a vertical nitride read-only memory (NROM) cell. A substrate having at least one trench is provided. A spacer is formed over the sidewall of the trench. Subsequently, ion implantation is performed on the substrate using the spacer as a mask to form doping areas as bit lines in the substrate near its surface and the bottom of the trench. Bit line oxides are formed over each of the doping areas. After the spacer is removed, a conformable insulating layer as gate dielectric is deposited on the sidewall of the trench and the surface of the bit line oxide. Finally, a conductive layer as a word line is deposited over the insulating layer and fills in the trench.

Abstract: A vertical DRAM and fabrication method thereof. The vertical DRAM has a plurality of memory cells on a substrate, and each of the memory cells has a trench capacitor, a vertical transistor, and a source-isolation oxide layer in a deep trench. The main advantage of the present invention is to form an annular source diffusion and an annular drain diffusion of the vertical transistor around the sidewall of the deep trench. As a result, when a gate of the transistor is turned on, an annular gate channel is provided. The width of the gate channel of the present invention is therefore increased.

Abstract: A read-only memory cell (ROM) and a fabrication method thereof. The cell comprises a substrate, a plurality of bit lines, a plurality of bit line oxides, a gate dielectric layer and a word line. The bit lines are formed near the surface of the substrate. The bit line oxides are disposed over the bit lines. The gate dielectric layer is disposed over the substrate between the bit lines and further comprises a silicon-rich oxide layer. The word line is disposed over the bit line oxides and the gate dielectric layer.

Abstract: A stacked gate vertical flash memory and a fabrication method thereof. The stacked gate vertical flash memory comprises a semiconductor substrate with a trench, a source conducting layer formed on the bottom of the trench, an insulating layer formed on the source conducting layer, a gate dielectric layer formed on a sidewall of the trench, a conducting spacer covering the gate dielectric layer as a floating gate, an inter-gate dielectric layer covering the conducting spacer, and a control gate conducting layer filled in the trench.

Abstract: A multi-bit vertical memory cell and method of fabricating the same. The multi-bit vertical memory cell comprises a semiconductor substrate with a trench, a plurality of bit lines formed therein near its surface and the bottom trench respectively, a plurality of bit line insulating layers over each bit line, a silicon rich oxide layer conformably formed on the sidewall of the trench and the surface of the surface of the bit line insulating layer, and a word line over the silicon rich oxide layer, and the trench is filled with the word line.

Abstract: A read-only memory cell (ROM) and a fabrication method thereof. The cell comprises a substrate, a plurality of bit lines, a plurality of bit line oxides, a gate dielectric layer and a word line. The bit lines are formed near the surface of the substrate. The bit line oxides are disposed over the bit lines. The gate dielectric layer is disposed over the substrate between the bit lines and further comprises a silicon-rich oxide layer. The word line is disposed over the bit line oxides and the gate dielectric layer.

Abstract: The present invention discloses a multi-bit stacked-type non-volatile memory having a spacer-shaped floating gate and a manufacturing method thereof. The manufacturing method includes forming a patterned dielectric layer containing arsenic on a semiconductor substrate, wherein the patterned dielectric layer defines an opening as an active area. A dielectric spacer is formed on a side wall of the patterned dielectric layer and a gate dielectric layer is formed on the semiconductor substrate. A source/drain region is formed by thermal driving method making arsenic diffusion from the patterned dielectric layer into the semiconductor substrate. A spacer-shaped floating gate is formed on the side wall of the dielectric spacer and the gate dielectric layer. An interlayer dielectric layer is formed on the spacer-shaped floating gate. A control gate is formed on the interlayer dielectric layer and fills the opening of the active area.

Abstract: A stacked gate vertical flash memory and a fabrication method thereof. The stacked gate vertical flash memory comprises a semiconductor substrate with a trench, a source conducting layer formed on the bottom of the trench, an insulating layer formed on the source conducting layer, a gate dielectric layer formed on a sidewall of the trench, a conducting spacer covering the gate dielectric layer as a floating gate, an inter-gate dielectric layer covering the conducting spacer, and a control gate conducting layer filled in the trench.

Abstract: A method for forming a vertical nitride read-only memory cell. A substrate having at least one trench is provided. A first conductive layer is formed in the lower trench and insulated from the substrate to serve as a source line. A first doping region is formed in the substrate adjacent to the top of the first conductive layer. A first insulating layer is formed on the first conductive layer. A second doping region is formed in the substrate adjacent to the top of the trench. A second insulating layer is formed over the sidewall of the trench and on the first insulating layer to serve as a gate dielectric layer. A second conductive layer is formed in the upper trench to serve as a control gate. A vertical nitride read-only memory cell is also disclosed.