Patents by Inventor Ching Wang

Ching Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10747273
    Abstract: An electronic device is provided, including a display module, a base and a camera module. The base has an upper shell member, and the display module is pivotally connected to the base and is rotatable relative to the base. The camera module is disposed on the upper shell of the base and can be switched between a closed mode and an open mode. The camera module has a lens. When the camera module is switched from the closed mode to the open mode, the camera module protrudes from the upper surface of the upper case member, and the optical axis of the lens is inclined toward the upper surface.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: August 18, 2020
    Assignee: QUANTA COMPUTER INC.
    Inventors: Yen-Ching Wang, Chia-Heng Cheng, Chia-Fu Lu
  • Publication number: 20200258864
    Abstract: A display device includes a first substrate, a first active element layer, first to third light-emitting elements, a first pixel defining layer, and fourth to sixth light-emitting elements. The first active element layer is disposed on the first substrate. The first, second and third light-emitting elements are electrically connected with the first active element layer. The first, second and third light-emitting elements have first, second and third light-emitting layers respectively. The first pixel defining layer is disposed on the first active element layer and has first, second and third openings. The first, second and third light-emitting layers are disposed in the first, second and third openings respectively. The fourth, fifth and sixth light-emitting elements are disposed on the first pixel defining layer. A vertical distance between the first light-emitting element and the fourth light-emitting element is greater than 0 micrometers and less than or equal to 5 micrometers.
    Type: Application
    Filed: July 26, 2019
    Publication date: August 13, 2020
    Applicant: Au Optronics Corporation
    Inventors: Yu-Ching Wang, Yi-Hui Lin
  • Patent number: 10734325
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first overlay grating over a substrate. The method includes forming a layer over the first overlay grating. The method includes forming a second overlay grating over the layer. The second overlay grating has a third strip portion and a fourth strip portion, the third strip portion and the fourth strip portion are elongated in the first elongated axis and are spaced apart from each other, there is a second distance between a third sidewall of the third strip portion and a fourth sidewall of the fourth strip portion, the third sidewall faces away from the fourth strip portion, the fourth sidewall faces the third strip portion, the first distance is substantially equal to the second distance, and the first trench extends across the third strip portion and the fourth strip portion.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Long-Yi Chen, Jia-Hong Chu, Chi-Wen Lai, Chia-Ching Liang, Kai-Hsiung Chen, Yu-Ching Wang, Po-Chung Cheng, Hsin-Chin Lin, Meng-Wei Chen, Kuei-Shun Chen
  • Patent number: 10725090
    Abstract: A method that is disclosed that includes the operations outlined below. Dies are arranged on a test fixture, and each of the dies includes first antennas and at least one via array, wherein the at least one via array is formed between at least two of the first antennas to separate the first antennas. By the first antennas of the dies, test processes are sequentially performed on an under-test device including second antennas that positionally correspond to the first antennas, according to signal transmissions between the first antennas and the second antennas.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Sen-Kuei Hsu, Chuan-Ching Wang, Hao Chen
  • Publication number: 20200225551
    Abstract: A reflective display device includes a thin-film transistor (TFT) array substrate, a front panel laminate (FPL), a front protection sheet, a back protection sheet, a light blocking layer, and a light source. The front panel laminate is located on the TFT array substrate, and has a transparent conductive layer and a display medium layer. The display medium layer is located between the transparent conductive layer and the TFT array substrate. The front protection sheet is located on the front panel laminate. The back protection sheet is located below the TFT array substrate. The light blocking layer at least covers a lateral surface of the back protection sheet. The light source faces toward a lateral surface of the front panel laminate, a lateral surface of the TFT array substrate, and the lateral surface of the back protection sheet.
    Type: Application
    Filed: July 24, 2019
    Publication date: July 16, 2020
    Inventors: Chia-Chi CHANG, Chih-Chun CHEN, Chi-Ming WU, Yi-Ching WANG, Jia-Hung CHEN, Cheng-Hsien LIN
  • Patent number: 10697194
    Abstract: A light-emitting warning rope is provided with one end connected to a tent and other end connected to an anchoring point. The light-emitting warning rope is disposed between the anchoring point and the tent to provide a tension to set the tent upright. The rope comprises a light-emitting core and a structural rope. The structural rope comprises a plurality of bearing yarns which is knitted into a strip body with the light-emitting core as an axis, and the strip body knitted by each bearing yarn is knitted in a mesh shape on the radial side and has a plurality of gaps through which light from the light-emitting core is transmitted. In any segment of the rope, the light-emitting core has a stretching length less than that of each bearing yarn, so that the axial tension acts substantially on the bearing yarns when the rope suffers an axial tension.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: June 30, 2020
    Assignee: Profilm Materials Ltd.
    Inventor: Ching Wang
  • Publication number: 20200194395
    Abstract: A semiconductor package has a plurality of pillars or portions of a plurality of lead strips, a plurality of semiconductor devices, one or two molding encapsulations and a plurality of electrical interconnections. The semiconductor package excludes a wire. The semiconductor package excludes a clip. A method is applied to fabricate semiconductor packages. The method includes providing a removable carrier; forming a plurality of pillars or a plurality of lead strips; attaching a plurality of semiconductor devices; forming one or two molding encapsulations; forming a plurality of electrical interconnections and removing the removable carrier. The method may further include a singulation process.
    Type: Application
    Filed: December 18, 2018
    Publication date: June 18, 2020
    Applicant: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Xiaotian Zhang, Yan Xun Xue, Long-Ching Wang, Yueh-Se Ho, Zhiqiang Niu
  • Publication number: 20200194347
    Abstract: A semiconductor package has a plurality of pillars or portions of a plurality of lead strips, a plurality of semiconductor devices, one or two molding encapsulations and a plurality of electrical interconnections. The semiconductor package excludes a wire. The semiconductor package excludes a clip. A method is applied to fabricate semiconductor packages. The method includes providing a removable carrier; forming a plurality of pillars or a plurality of lead strips; attaching a plurality of semiconductor devices; forming one or two molding encapsulations; forming a plurality of electrical interconnections and removing the removable carrier. The method may further include a singulation process.
    Type: Application
    Filed: December 18, 2018
    Publication date: June 18, 2020
    Applicant: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Yan Xun Xue, Xiaotian Zhang, Long-Ching Wang, Yueh-Se Ho, Zhiqiang Niu
  • Patent number: 10685474
    Abstract: The present invention provides a method for repairing incomplete 3D depth image using 2D image information. The method includes the following steps: obtaining 2D image information and 3D depth image information; dividing 2D image information into 2D reconstruction blocks and 2D reconstruction boundaries, and corresponding to 3D reconstruction of blocks and 3D reconstruction boundaries; analyzing each 3D reconstruction block, partitioning into residual-surface blocks and repaired blocks; and proceeding at least one 3D image reconstruction, which extends with the initial depth value of the 3D depth image of each of the residual-surface block and covers all the corresponding repaired block to form a repair block and to achieve the purpose of repairing incomplete 3D depth images using 2D image information.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: June 16, 2020
    Assignee: NATIONAL CENTRAL UNIVERSITY
    Inventors: Yeh-Wei Yu, Chi-Chung Lau, Ching-Cherng Sun, Tsung-Hsun Yang, Tzu-Kai Wang, Jia-Ching Wang, Chien-Yao Wang, Kuan-Chung Wang
  • Publication number: 20200152599
    Abstract: A method of manufacturing a semiconductor structure is provided. The method includes providing a first substrate including a plurality of conductive bumps disposed over the first substrate; providing a second substrate; disposing a patterned adhesive over the first substrate, wherein at least a portion of the plurality of conductive bumps is exposed through the patterned adhesive; bonding the first substrate with the second substrate; and singulating a chip from the first substrate.
    Type: Application
    Filed: January 14, 2020
    Publication date: May 14, 2020
    Inventors: ALEXANDER KALNITSKY, YI-YANG LEI, HSI-CHING WANG, CHENG-YU KUO, TSUNG LUNG HUANG, CHING-HUA HSIEH, CHUNG-SHI LIU, CHEN-HUA YU, CHIN-YU KU, DE-DUI LIAO, KUO-CHIO LIU, KAI-DI WU, KUO-PIN CHANG, SHENG-PIN YANG, ISAAC HUANG
  • Patent number: 10639476
    Abstract: An electronic stimulation device is adapted for electrically stimulating a target zone of an organism. The electronic stimulation device comprises at least one electronic stimulation unit. The electronic stimulation unit includes at least one first electrode and at least one second electrode. The electronic stimulation unit receives an electrical stimulation signal to impel the first electrode and the second electrode to generate an electric field. The range of the electric field covers the target zone, and the electric field strength ranges from 100 V/m to 1000 V/m. The electronic stimulation unit comprises a plurality of subunits and each subunit comprises at least one first electrode and at least one second electrode. An electronic stimulation system and the manufacturing method thereof are also provided.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: May 5, 2020
    Assignee: GIMER MEDICAL CO., LTD.
    Inventors: Chi-Heng Chang, Mei-Ching Wang
  • Patent number: 10630080
    Abstract: A charger comprises a housing, a first multi-layer printed circuit board (PCB), a second multi-layer PCB, and a third multi-layer PCB. The first PCB comprises at least a portion of a primary side circuit. The second PCB comprises at least a portion of a secondary side circuit. The third PCB is perpendicular to the first PCB and the second PCB. An isolation coupling element is disposed on the third PCB. The isolation coupling element comprises a multi-layer PCB. The first PCB comprises a high voltage (HV) semiconductor package. A surface of a die paddle of the HV semiconductor package is exposed from a molding encapsulation of the HV semiconductor package.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: April 21, 2020
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Pei-Lun Huang, Yu-Ming Chen, Tien-Chi Lin, Jung-Pei Cheng, Yueh-Ping Yu, Zhi-Qiang Niu, Xiaotian Zhang, Long-Ching Wang
  • Patent number: 10622077
    Abstract: A decoding method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The decoding method includes: reading first data from memory cells of the rewritable non-volatile memory module, wherein the first data includes a first bit stored in a first memory cell; obtaining a storage state of at least one second memory cell which is different from the first memory cell; obtaining first reliability information corresponding to the first bit according to the storage state of the second memory cell, wherein the first reliability information is different from default reliability information corresponding to the first bit; and decoding the first data according to the first reliability information. Therefore, a decoding efficiency can be improved.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: April 14, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Cheng Hsu, Szu-Wei Chen, Tien-Ching Wang
  • Patent number: 10614553
    Abstract: The present invention provides a method for Spherical Camera Image Stitching. By using two fisheye lens to catch two fisheye images and then being developed into three pairs of flat figures based on Segmented Sphere Projection (SSP) method. Thereafter each corresponding pair is stitched based on a similar-edge method, and then three pairs are combined to form a panoramic image. At the end, the combined panoramic image is projected to a 3-D ball sphere space.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: April 7, 2020
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Shih Ching Wang, Hsueh Ming Hang, Shaw Hwa Hwang
  • Patent number: 10593246
    Abstract: A pixel array substrate includes a substrate, first and second scan lines, data lines, and pixel structures. The first and second scan lines are disposed alternately and are enabled for different time durations in the same frame time. The data lines intersect with the first and second scan lines. Each of the pixel structures includes first and second active devices, and a pixel electrode. The first and second active devices are turned on and off by the first and second scan lines, respectively. The pixel electrode is connected to the first active device which is connected to one of the data lines by being connected to the second active device. A distance between the first and second scan lines adjacent to each other is a third to a half of a pitch of the pixel structures.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: March 17, 2020
    Assignee: E Ink Holdings Inc.
    Inventors: Shu-Fen Tsai, Jia-Hung Chen, Kuang-Heng Liang, Chih-Ching Wang, Ian French
  • Publication number: 20200061179
    Abstract: The present invention provides immunogenic compositions having one or more polysaccharide-protein conjugates in which polysaccharides obtained from bacterial capsules are conjugated to diphtheria toxin fragment B (DTFB) or a variant thereof. The immunogenic compositions may be multivalent pneumococcal polysaccharide conjugate compositions in which polysaccharides from one or more Streptococcus pneumoniae serotypes are conjugated to diphtheria toxin fragment B (DTFB) and, optionally, additional polysaccharides from one or more different Streptococcus pneumoniae serotypes are conjugated to one or more other carrier proteins.
    Type: Application
    Filed: February 20, 2018
    Publication date: February 27, 2020
    Applicant: Merck Sharp & Dohme Corp.
    Inventors: John E. MacNair, Michael A. Winters, Thomas Svab, Sheng-Ching Wang, William J. Smith, Cecilia Giovarelli
  • Publication number: 20200058595
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first overlay grating over a substrate. The method includes forming a layer over the first overlay grating. The method includes forming a second overlay grating over the layer. The second overlay grating has a third strip portion and a fourth strip portion, the third strip portion and the fourth strip portion are elongated in the first elongated axis and are spaced apart from each other, there is a second distance between a third sidewall of the third strip portion and a fourth sidewall of the fourth strip portion, the third sidewall faces away from the fourth strip portion, the fourth sidewall faces the third strip portion, the first distance is substantially equal to the second distance, and the first trench extends across the third strip portion and the fourth strip portion.
    Type: Application
    Filed: October 24, 2019
    Publication date: February 20, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Long-Yi CHEN, Jia-Hong CHU, Chi-Wen LAI, Chia-Ching LIANG, Kai-Hsiung CHEN, Yu-Ching WANG, Po-Chung CHENG, Hsin-Chin LIN, Meng-Wei CHEN, Kuei-Shun CHEN
  • Publication number: 20200052243
    Abstract: Provided is a protective structure including an auxiliary layer and a hard coating layer. The auxiliary layer has a first surface and a second surface opposite to the first surface. The hard coating layer is located on the second surface of the auxiliary layer. The Young's modulus of the auxiliary layer is gradually increased from the second surface to the first surface. An electronic device with the same is also provided.
    Type: Application
    Filed: April 10, 2019
    Publication date: February 13, 2020
    Applicants: Industrial Technology Research Institute, Intellectual Property Innovation Corporation
    Inventors: Yung-Hui Yeh, Jui-Chang Chuang, Li-Ching Wang, Cheng-Yueh Chang, Chyi-Ming Leu, Shih-Ming Chen
  • Publication number: 20200035013
    Abstract: The present invention provides a method for repairing incomplete 3D depth image using 2D image information. The method includes the following steps: obtaining 2D image information and 3D depth image information; dividing 2D image information into 2D reconstruction blocks and 2D reconstruction boundaries, and corresponding to 3D reconstruction of blocks and 3D reconstruction boundaries; analyzing each 3D reconstruction block, partitioning into residual-surface blocks and repaired blocks; and proceeding at least one 3D image reconstruction, which extends with the initial depth value of the 3D depth image of each of the residual-surface block and covers all the corresponding repaired block to form a repair block and to achieve the purpose of repairing incomplete 3D depth images using 2D image information.
    Type: Application
    Filed: November 19, 2018
    Publication date: January 30, 2020
    Inventors: Yeh-Wei YU, Chi-Chung LAU, Ching-Cherng SUN, Tsung-Hsun YANG, Tzu-Kai WANG, Jia-Ching WANG, Chien-Yao WANG, Kuan-Chung WANG
  • Patent number: D878602
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: March 17, 2020
    Assignee: GIMER MEDICAL CO., LTD.
    Inventors: Chi-Heng Chang, Mei-Ching Wang