Patents by Inventor Ching-Yu Chang

Ching-Yu Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10520820
    Abstract: The present disclosure provides NTD developers and corresponding lithography techniques that can overcome resolution, line edge roughness (LER), and sensitivity (RLS) tradeoff barriers particular to extreme ultraviolet (EUV) technologies, thereby achieving high patterning fidelity for advanced technology nodes. An exemplary lithography method includes forming a negative tone resist layer over a workpiece; exposing the negative tone resist layer to EUV radiation; and removing an unexposed portion of the negative tone resist layer in a negative tone developer, thereby forming a patterned negative tone resist layer. The negative tone developer includes an organic solvent having a log P value greater than 1.82. The organic solvent is an ester acetate derivative represented by R1COOR2. R1 and R2 are hydrocarbon chains having four or less carbon atoms. In some implementations, R1, R2, or both R1 and R2 are propyl functional groups, such as n-propyl, isopropyl, or 2-methylpropyl.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Yu Liu, Wei-Han Lai, Tzu-Yang Lin, Ming-Hui Weng, Ching-Yu Chang, Chin-Hsiang Lin
  • Patent number: 10520833
    Abstract: Semiconductor systems, apparatuses and methods are provided. In one embodiment, an extreme ultraviolet lithography system includes a substrate stage configured to secure a substrate at a first vertical level, wherein the substrate is deposited with a resist layer thereon; at least one electrode positioned at a second vertical level above the first vertical level; and a power source configured to apply an electric field across the at least one electrode and the substrate stage, including across a thickness of the resist layer when the substrate is secured on the substrate stage.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Hui Weng, Cheng-Han Wu, Ching-Yu Chang, Chin-Hsiang Lin
  • Patent number: 10520821
    Abstract: The present disclosure provides a method for lithography patterning. The method includes coating a bottom layer on a substrate, wherein the bottom layer includes a carbon-rich material; forming a middle layer on the bottom layer, wherein the middle layer has a composition such that its silicon concentration is enhanced to be greater than 42% in weight; coating a photosensitive layer on the middle layer; performing an exposing process to the photosensitive layer; and developing the photosensitive layer to form a patterned photosensitive layer.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Yu Liu, Ching-Yu Chang, Chin-Hsiang Lin
  • Patent number: 10520836
    Abstract: Immersion lithography system and method using a sealed wafer bottom are described. One embodiment is an immersion lithography apparatus comprising a lens assembly comprising an imaging lens and a wafer stage for retaining a wafer beneath the lens assembly, the wafer stage comprising a seal ring disposed on a seal ring frame along a top edge of the wafer retained on the wafer stage, the seal ring for sealing a gap between an edge of the wafer and the wafer stage. The embodiment further includes a fluid tank for retaining immersion fluid, the fluid tank situated with respect to the wafer stage for enabling full immersion of the wafer retained on the wafer stage in the immersion fluid and a cover disposed over at least a portion of the fluid tank for providing a temperature-controlled, fluid-rich environment within the fluid tank.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Burn Jeng Lin, Ching-Yu Chang
  • Patent number: 10520822
    Abstract: The present disclosure provides lithography resist materials and corresponding lithography techniques for improving lithography resolution, in particular, by reducing swelling of resist layers during development. An exemplary lithography method includes performing a treatment process on a resist layer to cause cross-linking of acid labile group components of the resist layer via cross-linkable functional components, performing an exposure process on the resist layer, and performing a development process on the resist layer. In some implementations, the resist layer includes an exposed portion and an unexposed portion after the exposure process, and the treatment process reduces solubility of the unexposed portion to a developer used during the development process by increasing a molecular weight of a polymer in the unexposed portion. The treatment process is performed before or after the exposure process.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Hui Weng, Cheng-Han Wu, Ching-Yu Chang, Chin-Hsiang Lin
  • Patent number: 10517179
    Abstract: Provided is a material composition and method that includes forming a patterned resist layer on a substrate. The patterned resist layer has a first pattern width, and the patterned resist layer has a first pattern profile having a first proportion of active sites. In some examples, the patterned resist layer is coated with a treatment material. In some embodiments, the treatment material bonds to surfaces of the patterned resist layer to provide a treated patterned resist layer having a second pattern profile with a second proportion of active sites greater than the first proportion of active sites. By way of example, and as part of the coating the patterned resist layer with the treatment material, a first pattern shrinkage process may be performed, where the treated patterned resist layer has a second pattern width less than a first pattern width.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Siao-Shan Wang, Cheng-Han Wu, Ching-Yu Chang, Chin-Hsiang Lin
  • Patent number: 10514603
    Abstract: Shrinkage and mass losses are reduced in photoresist exposure and post exposure baking by utilizing a small group which will decompose. Alternatively a bulky group which will not decompose or a combination of the small group which will decompose along with the bulky group which will not decompose can be utilized. Additionally, polar functional groups may be utilized in order to reduce the diffusion of reactants through the photoresist.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Han Lai, Ching-Yu Chang, Chen-Hau Wu
  • Patent number: 10515847
    Abstract: A method for forming openings in an underlayer includes: forming a photoresist layer on an underlayer formed on a substrate; exposing the photoresist layer; forming photoresist patterns by developing the exposed photoresist layer, the photoresist patterns covering regions of the underlayer in which the openings are to be formed; forming a liquid layer over the photoresist patterns; after forming the liquid layer, performing a baking process so as to convert the liquid layer to an organic layer in a solid form; performing an etching back process to remove a portion of the organic layer on a level above the photoresist patterns; removing the photoresist patterns, so as to expose portions of the underlayer by the remaining portion of the organic layer; forming the openings in the underlayer by using the remaining portion of the organic layer as an etching mask; and removing the remaining portion of the organic layer.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tzu-Yang Lin, Cheng-Han Wu, Ching-Yu Chang, Chin-Hsiang Lin
  • Patent number: 10515812
    Abstract: A method includes forming a metal-containing material layer over a substrate, patterning the metal-containing material layer, where the patterned material layer has an average roughness, and electrochemically treating the patterned metal-containing material layer to reduce the average roughness. The treatment may be implemented by exposing the patterned metal-containing material layer to an electrically conducting solution, and applying a potential between the patterned material layer and a counter electrode exposed to the solution, such that the treating reduces the average roughness of the patterned material layer. The electrically conducting solution may include an ionic compound dissolved in water, alcohol, and/or a surfactant.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Wei Wang, Joy Cheng, Ching-Yu Chang, Chin-Hsiang Lin
  • Publication number: 20190384171
    Abstract: A photoresist composition includes a photoresist material including metal oxide nanoparticles and a ligand, and an acid having an acid dissociation constant, pKa, of ?15<pKa<4, or a base having a pKa of 40>pKa>9.
    Type: Application
    Filed: November 20, 2018
    Publication date: December 19, 2019
    Inventors: An-Ren ZI, Chin-Hsiang LIN, Ching-Yu CHANG
  • Publication number: 20190384177
    Abstract: The present disclosure provides a method for lithography patterning in accordance with some embodiments. The method includes forming a material layer on a substrate; forming a blocking layer on the material layer, wherein a bottom portion of the blocking layer reacts with the material layer, resulting in a capping layer that seals the material layer from an upper portion of the blocking layer. The method further includes forming a photoresist layer on the blocking layer; exposing the photoresist layer; and developing the photoresist layer, resulting in a patterned photoresist layer.
    Type: Application
    Filed: August 23, 2019
    Publication date: December 19, 2019
    Inventors: Siao-Shan Wang, Chen-Yu Liu, Ching-Yu Chang, Chin-Hsiang Lin
  • Publication number: 20190384170
    Abstract: A method of forming a photoresist pattern includes forming a protective layer over a photoresist layer formed on a substrate, and selectively exposing the protective layer and the photoresist layer to actinic radiation. The protective layer and the photoresist layer are developed to form a pattern in the photoresist layer, and the protective layer is removed. The protective layer includes a polymer having pendant fluorocarbon groups and pendant acid leaving groups.
    Type: Application
    Filed: October 17, 2018
    Publication date: December 19, 2019
    Inventors: An-Ren ZI, Chin-Hsiang LIN, Ching-Yu CHANG
  • Publication number: 20190385902
    Abstract: Semiconductor devices and methods of forming semiconductor devices are provided. A method includes forming a first mask layer over an underlying layer, patterning the first mask layer to form a first opening, forming a non-conformal film over the first mask layer, wherein a first thickness of the non-conformal film formed on the top surface of the first mask layer is greater than a second thickness of the non-conformal film formed on a sidewall surface of the first mask layer, performing a descum process, wherein the descum process removes a portion of the non-conformal film within the first opening, and etching the underlying layer using the patterned first mask layer and remaining portions of the non-conformal film as an etching mask.
    Type: Application
    Filed: June 15, 2018
    Publication date: December 19, 2019
    Inventors: Wei-Ren Wang, Shing-Chyang Pan, Ching-Yu Chang, Wan-Lin Tsai, Jung-Hau Shiu, Tze-Liang Lee
  • Publication number: 20190384173
    Abstract: A photoresist layer is formed over a wafer. The photoresist layer includes a metallic photoresist material and one or more additives. An extreme ultraviolet (EUV) lithography process is performed using the photoresist layer. The one or more additives include: a solvent having a boiling point greater than about 150 degrees Celsius, a photo acid generator, a photo base generator, a quencher, a photo de-composed base, a thermal acid generator, or a photo sensitivity cross-linker.
    Type: Application
    Filed: June 15, 2018
    Publication date: December 19, 2019
    Inventors: An-Ren Zi, Joy Cheng, Ching-Yu Chang
  • Publication number: 20190385816
    Abstract: An embodiment is an apparatus, such as a plasma chamber. The apparatus includes chamber walls and a chamber window defining an enclosed space. A chamber window is disposed between a plasma antenna and a substrate support. A gas delivery source is mechanically coupled to the chamber window. The gas delivery source comprises a gas injector having a passageway, a window at a first end of the passageway, and a nozzle at a second end of the passageway. The nozzle of the gas delivery source is disposed in the enclosed space. A fastening device is mechanically coupled to the gas delivery source. The fastening device is adjustable to adjust a sealing force against the gas injector.
    Type: Application
    Filed: June 13, 2018
    Publication date: December 19, 2019
    Inventors: Yung-Shun Hsu, Ching-Yu Chang, Chiao-Kai Chang, Wai Hong Cheah, Chien-Fang Lin
  • Publication number: 20190378800
    Abstract: An overlay mark includes a first feature extending in an X-direction, wherein the first feature is a first distance from a substrate. The overlay mark further includes a second feature extending in a Y-direction perpendicular to the X-direction, wherein the second feature is a second distance from the substrate, and the second distance is different from the first distance. The overlay mark further includes a third feature extending in the X-direction and the Y-direction, wherein the third feature is a third distance from the substrate, and the third distance is different from the first distance and the second distance.
    Type: Application
    Filed: August 21, 2019
    Publication date: December 12, 2019
    Inventors: Chen-Yu CHEN, Ming-Feng SHIEH, Ching-Yu CHANG
  • Patent number: 10503070
    Abstract: Methods and materials directed to a photosensitive material and a method of performing a lithography process using the photosensitive material are described. A semiconductor substrate is provided. A layer including an additive component is formed over the semiconductor substrate. The additive component includes a metal cation. One or more bonds are formed to bond the metal cation and one or more anions. Each of the one or more anions is one of a protecting group and a polymer chain bonding component. The polymer chain bonding component is bonded to a polymer chain of the layer. The layer is exposed to a radiation beam.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: December 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: An-Ren Zi, Ching-Yu Chang, Chien-Wei Wang
  • Publication number: 20190371600
    Abstract: A method includes forming a photoresist layer over a substrate, where the photoresist layer includes a polymer blended with a photo-acid generator (PAG), exposing the photoresist layer to a radiation source, and developing the photoresist layer, resulting in a patterned photoresist layer. The PAG is bonded to one or more polarity-enhancing group (PEG), which is configured to increase a dipole moment of the PAG. The exposing may separate the PAG into a cation and an anion, such that a PEG bonded to the cation and a PEG bonded to the anion each increases a polarity of the cation and the anion, respectively.
    Type: Application
    Filed: May 31, 2018
    Publication date: December 5, 2019
    Inventors: Ya-Ching Chang, Ching-Yu Chang, Chin-Hsiang Lin, Yen-Hao Chen
  • Publication number: 20190346766
    Abstract: Shrinkage and mass losses are reduced in photoresist exposure and post exposure baking by utilizing a small group which will decompose. Alternatively a bulky group which will not decompose or a combination of the small group which will decompose along with the bulky group which will not decompose can be utilized. Additionally, polar functional groups may be utilized in order to reduce the diffusion of reactants through the photoresist.
    Type: Application
    Filed: July 29, 2019
    Publication date: November 14, 2019
    Inventors: Wei-Han Lai, Ching-Yu Chang, Chen-Hau Wu
  • Patent number: 10466593
    Abstract: A method of making a semiconductor device is provided. The method includes forming a photoresist material over a substrate, the photoresist material having a polymer that includes a backbone having a segment and a linking group, the segment including a carbon chain and an ultraviolet (UV) curable group, the UV curable group coupled to the carbon chain and to the linking group; performing a first exposure process that breaks the backbone of the polymer via decoupling the linking group from the connected UV curable group of each segment; performing a second exposure process to form a patterned photoresist layer; and developing the patterned photoresist layer.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: November 5, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: An-Ren Zi, Ching-Yu Chang