Abstract: Technology for an Information Centric Networking gateway (ICN-GW) operable to modify an ICN message received from a user equipment (UE) in a Fifth Generation (5G) cellular network is disclosed. The ICN-GW can decode the ICN message received from the UE via a Next 5 Generation NodeB (gNB) and an ICN point of attachment (ICNPoA). The ICN-GW can modify the ICN message to produce a modified ICN message. The ICN-GW can encode the modified ICN message to route the modified ICN message to a data network.

Abstract: Systems, apparatuses, methods, and computer-readable media are provided for a user equipment (UE) of a wireless communication system. The UE includes a processor circuitry, and radio front end circuitry coupled to the processor circuitry. The processor circuitry is configured to determine and indicate, to a core network via a radio access network (RAN), one or more cellular internet of things (CIoT) features that are required by the UE and CIoT network behavior expected from the core network to support the one or more CIoT features that are required by the UE. The processor circuitry is configured to select either an enhanced packet core (EPC) or a 5G core (5GC) to establish a wireless connection with the core network, based on a first set of CIoT features supported by the EPC and a second set of CIoT features supported by the 5GC received from the core network.

Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.

Abstract: An unmanned aerial vehicle can be configured to adjust a beam direction, provide path information, act as a base station, act as a cluster head, include an improved directional antenna or array of directional antennas, communicate in a collaboration using belief propagation, receive communications from a serving station aiding in navigation or improved signal performance, or the like.

Abstract: A method of forming a photoresist pattern includes forming a protective layer over a photoresist layer formed on a substrate. The protective layer and the photoresist layer are selectively exposed to actinic radiation. The photoresist layer is developed to form a pattern in the photoresist layer. The protective layer includes a polymer without a nitrogen-containing moiety, and a basic quencher, an organic acid, a photoacid generator, or a thermal acid generator.

Abstract: A semiconductor structure includes a barrier layer over a channel layer, and a doped layer over the barrier layer. A gate electrode is over the doped layer and a doped interface layer is formed between the barrier layer and the doped layer. The doped interface layer includes a dopant and a metal. The metal has a metal concentration that follows a gradient function from a highest metal concentration to a lowest metal concentration.

Abstract: A method of manufacturing a bump structure includes forming a passivation layer over a substrate. A metal pad structure is formed over the substrate, wherein the passivation layer surrounds the metal pad structure. A polyimide layer including a polyimide is formed over the passivation layer and the metal pad structure. A metal bump is formed over the metal pad structure and the polyimide layer. The polyimide is a reaction product of a dianhydride and a diamine, wherein at least one of the dianhydride and the diamine comprises one selected from the group consisting of a cycloalkane, a fused ring, a bicycloalkane, a tricycloalkane, a bicycloalkene, a tricycloalkene, a spiroalkane, and a heterocyclic ring.

Abstract: A method includes bonding a first device die to a second device die through face-to-face bonding, wherein the second device die is in a device wafer, forming a gap-filling region to encircle the first device die, performing a backside-grinding process on the device wafer to reveal a through-via in the second device die, and forming a redistribution structure on the backside of the device wafer. The redistribution structure is electrically connected to the first device die through the through-via in the second device die. A supporting substrate is bonded to the first device die.

Abstract: A photoresist includes a polymer and a photoactive compound. The photoactive compound contains a sensitizer component. The photoactive compound contains an acid generator or a base molecular. The acid generator or the base molecular bonds the sensitizer component. The photoactive compound is within a polymer backbone. The sensitizer component is configured to absorb an EUV light to produce electrons.

Abstract: A device includes a first row of active areas, a second row of active areas, and a first power via. The first row of active areas includes first active areas that extend in a first direction and second active areas that extend in the first direction. Each of the first active areas has a first width in a second direction and each of the second active areas has a second width in the second direction that is smaller than the first width. The second row of active areas is situated above or below the first row of active areas and includes third active areas that extend in the first direction. Each of the third active areas has the second width in the second direction. The first power via extends in a third direction between a transistor level of the device and a backside metal layer of the device and is situated between the first row of active areas and the second row of active areas.

Abstract: A system includes a processor, and a display, a reader, a switch, a scale, a memory device, intake-type buttons and output-type buttons that are connected to the processor. The processor controls the display to display an identification number obtained by using the reader to read an identifier. The switch is operated to enable the processor to operate in an intake mode or an output mode. When operating in the intake (output) mode, the processor controls the display to display a symbol corresponding to one of the intake-type (output-type) buttons that is determined to be pressed, and in response to receipt of weight data from the scale, controls the display to display a value of pre-intake (post-output) weight obtained based on the weight data, and stores the value of pre-intake (post-output) weight in the memory device.

Abstract: The present disclosure provides a method for lithography patterning in accordance with some embodiments. The method includes forming a photoresist layer over a substrate, wherein the photoresist layer includes a metal-containing chemical; performing an exposing process to the photoresist layer; and performing a first developing process to the photoresist layer using a first developer, thereby forming a patterned resist layer, wherein the first developer includes a first solvent and a chemical additive to remove metal residuals generated from the metal-containing chemical.

Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate, exposing the photoresist layer to an EUV radiation, developing the photoresist layer to form a patterned photoresist, forming a coating layer on the patterned photoresist, and after forming the coating layer on the patterned photoresist, etching the substrate using a combination of the coating layer and the patterned photoresist as an etching mask.

Abstract: In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

Abstract: A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.

Abstract: A method of forming a patterned photoresist layer includes the following operations: (i) forming a patterned photoresist on a substrate; (ii) forming a molding layer covering the patterned photoresist; (iii) reflowing the patterned photoresist in the molding layer; and (iv) removing the molding layer from the reflowed patterned photoresist. In some embodiments, the molding layer has a glass transition temperature that is greater than or equal to the glass transition temperature of the patterned photoresist. In yet some embodiments, the molding layer has a glass transition temperature that is 3° C.-30° C. less than the glass transition temperature of the patterned photoresist.

Abstract: In one embodiment, an apparatus of a User Equipment (UE) device includes memory storing non-public network (NPN) configuration information, a radio frequency (RF) interface, and processing circuitry coupled to the memory and the RF interface. The RF interface receives information broadcast by a radio access network (RAN) node of the particular NPN, where the information includes a NPN indicator indicating that the RAN node supports a NPN and NPN service information indicating services supported by the particular NPN. The processing circuitry establishes, in response to detecting the NPN indicator in the information received from the RAN node, a connection to the particular NPN based on the NPN configuration information and the NPN service information received from the RAN node.

Abstract: A method of forming a semiconductor device includes forming a photoresist layer over a mask layer, patterning the photoresist layer, and forming an oxide layer on exposed surfaces of the patterned photoresist layer. The mask layer is patterned using the patterned photoresist layer as a mask. A target layer is patterned using the patterned mask layer as a mask.

Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate, a first active region disposed on the substrate, a first gate structure disposed on the first active region, and a second gate structure disposed on the first active region and spaced apart from the first gate structure. The first active region includes a first portion and a second portion, the first portion of the first active region and the second portion of the first active region collectively specify a first stair profile. The first stair profile is located between the first gate structure and the second gate structure from a top view.

Abstract: Provided is a microfluidic detection device, including a base with a microfluidic channel structure formed on the base and a lid covering the base. The microfluidic channel structure includes a sample well for loading a sample, a detection well having a first reagent for reacting with the sample, and a channel connecting the sample well and the detection well. The detection well has a recess deeper than the channel, and the base includes a protrusion corresponding to the recess to form a space between the protrusion and the recess. Also provided is a method for rapid diagnostic testing by the microfluidic detection device.