Abstract: In an embodiment, a method includes: forming a first integrated circuit die, the first integrated circuit die comprising: a first active device along a first substrate; a first electrostatic discharge well along the first substrate; a first bonding pad over the first substrate and electrically connected to the first active device; and a first lightning conductor over the first substrate and electrically connected to the first electrostatic discharge well; forming a second integrated circuit die, the second integrated circuit die comprising: a second active device along a second substrate; a second electrostatic discharge well along the second substrate; a second bonding pad over the second substrate and electrically coupled to the second active device; and a second lightning conductor over the second substrate and electrically connected to the second electrostatic discharge well; and bonding the first integrated circuit die to the second integrated circuit die.

Abstract: In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

Abstract: In some embodiments, an integrated circuit device includes a substrate having a frontside and a backside; one or more active semiconductor devices formed on the frontside of the substrate; conductive paths formed on the frontside of the substrate; and conductive paths formed on the backside of the substrate. At least some of the conductive paths formed on the backside of the substrate, and as least some of the conductive paths formed on the front side of the substrate, are signal paths among the active semiconductor devices. In in some embodiments, other conductive paths formed on the backside of the substrate are power grid lines for powering at least some of the active semiconductor devices.

Abstract: A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.

Abstract: Method of forming pattern in photoresist layer includes forming photoresist layer over substrate, selectively exposing photoresist layer to actinic radiation forming latent pattern. Latent pattern is developed by applying developer to form pattern. Photoresist layer includes photoresist composition including polymer: A1, A2, L are direct bond, C4-C30 aromatic, C4-C30 alkyl, C4-C30 cycloalkyl, C4-C30 hydroxylalkyl, C4-C30 alkoxy, C4-C30 alkoxyl alkyl, C4-C30 acetyl, C4-C30 acetylalkyl, C4-C30 alkyl carboxyl, C4-C30 cycloalkyl carboxyl, C4-C30 hydrocarbon ring, C4-C30 heterocyclic, —COO—, A1 and A2 are not both direct bonds, and are unsubstituted or substituted with a halogen, carbonyl, or hydroxyl; A3 is C6-C14 aromatic, wherein A3 is unsubstituted or substituted with halogen, carbonyl, or hydroxyl; R1 is acid labile group; Ra, Rb are H or C1-C3 alkyl; Rf is direct bond or C1-C5 fluorocarbon; PAG is photoacid generator; 0<x/(x+y+z)<1, 0<y/(x+y+z)<1, and 0<z/(x+y+z)<1.

Abstract: A method of manufacturing a semiconductor device includes forming a first layer including an organic material over a substrate. A second layer including a reaction product of a silicon-containing material and a photoacid generator is formed over the first layer. A photosensitive layer is formed over the second layer, and the second layer is patterned.

Abstract: A photoresist layer is formed over a wafer. The photoresist layer includes a metallic photoresist material and one or more additives. An extreme ultraviolet (EUV) lithography process is performed using the photoresist layer. The one or more additives include: a solvent having a boiling point greater than about 150 degrees Celsius, a photo acid generator, a photo base generator, a quencher, a photo de-composed base, a thermal acid generator, or a photo sensitivity cross-linker.

Abstract: Examples described herein relate to an apparatus comprising: multiple processors and circuitry coupled to the multiple processors, wherein at least one of the multiple processors comprises multiple cores and wherein the circuitry is to provide the multiple processors with access to at least two firmware Trusted Platform Module (TPM) instances. At least two firmware TPM instances of the firmware TPM instances is to apply cryptography to store information for platform authentication and wherein the information for platform authentication comprises one or more of: user credentials, passwords, certificates, encryption keys, shared secrets, state information, or hash data.

Abstract: A semiconductor device may be manufactured using a multiple-layer photoresist that is formed of one or more materials that reduce the likelihood and/or amount of residual material retained in the multiple-layer photoresist. A photoresist underlayer of the multiple-layer photoresist includes a polymer having a highly uniform distribution of polar group monomers. Additionally and/or alternatively, the photoresist underlayer includes a polymer that includes a main chain and a plurality of side chains coupled with the main chain. The side chains include an acid generator component. Since the acid generator component is coupled with the main chain of the polymer by the side chains as opposed to uncontrollably diffusing into the photoresist layer, the acid generated by the acid generator component upon exposure to radiation collects under the bottom of the photoresist layer in a uniform manner and enables the bottommost portions of the photoresist layer to be developed and removed.

Abstract: A method of manufacturing a semiconductor device includes forming a first protective layer over an edge portion of a first main surface of a semiconductor substrate. A metal-containing photoresist layer is formed over the first main surface of the semiconductor substrate. The first protective layer is removed, and the metal-containing photoresist layer is selectively exposed to actinic radiation. A second protective layer is formed over the edge portion of the first main surface of the semiconductor substrate. The selectively exposed photoresist layer is developed to form a patterned photoresist layer, and the second protective layer is removed.

Abstract: A photo acid generator includes a photoactive cation and an anion. The photoactive cation includes a moiety and one or more EUV absorbing atoms. The moiety includes onium salts, selenium salts, phosphonium salts, iodonium salts, or sulfonium salts. The one or more EUV absorbing atoms are attached to the moiety. The anion is attached to the photoactive cation.

Abstract: A minimum IC operating voltage searching method includes acquiring a corner type of an IC, acquiring ring oscillator data of the IC, generating a first prediction voltage according to the corner type and the ring oscillator data by using a training model, generating a second prediction voltage according to the ring oscillator data by using a non-linear regression approach under an N-ordered polynomial, and generating a predicted minimum IC operating voltage according to the first prediction voltage and the second prediction voltage. N is a positive integer.

Abstract: A method for manufacturing a semiconductor device includes forming a resist structure including forming a resist layer including a resist composition over a substrate. After forming the resist layer, the resist layer is treated with an additive. The additive is one or more selected from the group consisting of a radical inhibitor, a thermal radical initiator, and a photo radical initiator.

Abstract: A gait evaluating system including a processor is provided. The processor identifies whether a gait type of the user belongs to a normal gait, a non-neuropathic gait or a neuropathic gait based on step feature values of a user and walking limb feature values of the user. In response to that the gait type of the user belongs to the non-neuropathic gait, the processor controls the display panel to display a first auxiliary information, a second auxiliary information, and a third auxiliary information. The first auxiliary information indicates a potential sarcopenia of the user. The second auxiliary information indicates a dietary guideline for muscle building and muscle strengthening. The third auxiliary information shows a motion instruction video for regaining or maintaining muscle strength of the user.

Abstract: Various embodiments herein provide techniques to enable communication between a user equipment (UE) microservice and a microservice of a wireless cellular network via service mesh. A first solution is described, in which the service mesh is in the network, and the network includes a service mesh proxy to communicate with the UE. A second solution is also described, in which the UE is part of the cellular network service mesh and includes a service mesh proxy in the UE. Other embodiments may be described and claimed.

Abstract: Technology for an Information Centric Networking gateway (ICN-GW) operable to modify an ICN message received from a user equipment (UE) in a Fifth Generation (5G) cellular network is disclosed. The ICN-GW can decode the ICN message received from the UE via a Next Generation NodeB (gNB) and an ICN point of attachment (ICN-PoA). The ICN-GW can modify the ICN message to produce a modified ICN message. The ICN-GW can encode the modified ICN message to route the modified ICN message to a data network.

Abstract: A wafer map recognition method using artificial intelligence includes obtaining wafer maps of a plurality of wafers; performing an unsupervised algorithm on the wafer map of each wafer in the plurality of wafers to generate a feature data set for the corresponding wafer map; and performing a clustering algorithm according to a plurality of feature data sets for the plurality of wafer maps to find a wafer map with a potential defect.

Abstract: A method includes illuminating radiation to a resist layer over a substrate to pattern the resist layer. The patterned resist layer is developed by using a positive tone developer. The patterned resist layer is rinsed using a basic aqueous rinse solution. A pH value of the basic aqueous rinse solution is lower than a pH value of the developer, and a rinse temperature of rinsing the patterned resist layer is in a range of about 20° C. to about 40° C.

Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate. A first precursor and a second precursor are combined. The first precursor is an organometallic having a formula: MaRbXc, where M is one or more of Sn, Bi, Sb, In, and Te, R is one or more of a C7-C11 aralkyl group, a C3-C10 cycloalkyl group, a C2-C10 alkoxy group, and a C2-C10 alkylamino group, X is one or more of a halogen, a sulfonate group, and an alkylamino group, and 1?a?2, b?1, c?1, and b+c?4, and the second precursor is one or more of water, an amine, a borane, and a phosphine. The photoresist layer is selectively exposed to actinic radiation to form a latent pattern. The latent pattern is developed by applying a developer to the selectively exposed photoresist layer.

Abstract: A photoresist composition includes a conjugated resist additive, a photoactive compound, and a polymer resin. The conjugated resist additive is one or more selected from the group consisting of a polyacetylene, a polythiophene, a polyphenylenevinylene, a polyfluorene, a polypryrrole, a polyphenylene, and a polyaniline. The polyacetylene, polythiophene, polyphenylenevinylene, polyfluorene, polypryrrole, the polyphenylene, and polyaniline includes a substituent selected from the group consisting of an alkyl group, an ether group, an ester group, an alkene group, an aromatic group, an anthracene group, an alcohol group, an amine group, a carboxylic acid group, and an amide group. Another photoresist composition includes a polymer resin having a conjugated moiety and a photoactive compound. The conjugated moiety is one or more selected from the group consisting of a polyacetylene, a polythiophene, a polyphenylenevinylene, a polyfluorene, a polypryrrole, a polyphenylene, and a polyaniline.