Abstract: A method includes the following steps. A target layer is formed on a substrate. A resist layer is formed on the target layer. The resist layer is exposed such that secondary electrons are produced in the resist layer. The secondary electrons are terminated using an additive. The resist layer is developed. The target layer is etched using the developed resist layer as a mask.

Abstract: In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

Abstract: A container for containing food or liquid is provided. The container includes a body portion, a lid and an attachment. The lid is detachably disposed on the body portion. The attachment includes a magnetic attraction member and a connecting structure. The magnetic attraction member is independent from the lid and adapted to be magnetically connected to a mobile electronic device. The connecting structure is disposed between the magnetic attraction member and the container for selectively fixing the magnetic attraction member at a first position or a second position. At least a portion of the connecting structure is fixed to the container.

Abstract: A method of manufacturing a semiconductor device includes the following operations. A metal oxide photoresist layer is formed over a target layer. The metal oxide photoresist layer comprises a metal oxide core with organic ligands, a metal oxide framework with organic ligands, or a combination thereof. The metal oxide photoresist layer is exposed to an extreme ultraviolet radiation. The metal oxide photoresist layer is treated with a ligand leaving promoter. The metal oxide photoresist layer is developed to form a patterned photoresist. The target layer is etched by using the patterned photoresist as an etching mask.

Abstract: A sport assistance system and a sport assistance method are provided. The sport assistance method includes: obtaining a real-time heart rate; executing a first assistance procedure according to a target heart rate, a maximum heart rate, a resting heart rate, a first media and the real-time heart rate; and executing a second assistance procedure according to the target heart rate and the real-time heart rate. The first assistance procedure includes: playing the first media at a first tempo rate; and adjusting the first tempo rate according to the real-time heart rate until the real-time heart rate is close to the target heart rate and a first scheduled time is met. The first initial value is greater than the resting heart rate. The second assistance procedure includes: playing a second media; and adjusting a second tempo rate according to an adjustment parameter until a second scheduled time is met.

Abstract: A method of forming semiconductor device includes depositing a coating layer over a substrate, forming a photoresist layer over the coating layer, exposing the photoresist layer to actinic radiation, and developing the photoresist layer to form a patterned photoresist layer. The coating layer includes a polymer containing a first unit having a pendant hydrogen donor group capable of producing a hydrogen radical upon exposure to the actinic radiation or heat, and a second unit having a pendant water donor group capable of producing water upon exposure to the actinic radiation or heat.

Abstract: An integrated circuit includes a first inverter and a first transmission gate constructed with wide type-one transistors and wide type-two transistors. The integrated circuit also includes a first clocked inverter constructed with narrow type-one transistors and narrow type-two transistors. A latch is formed with the first inverter and the first clocked inverter. The first transmission gate is connected to between an output of the first inverter. The wide type-one transistors are formed in a wide type-one active-region structure and the narrow type-one transistors are formed in a narrow type-one active-region structure. The wide type-two transistors are formed in a wide type-two active-region structure and the narrow type-two transistors are formed in in a narrow type-two active-region structure.

Abstract: A method includes attaching a front-side of a first die to a wafer, the first bond pad being along a back-side of the first die, the wafer comprising a substrate and a transistor along the substrate, the transistor facing the wafer, the first die comprising: a first bond pad; a first back-side interconnect structure; a first front-side interconnect structure; a first semiconductor substrate interposed between the first back-side interconnect structure and the first front-side interconnect structure; and a first transistor along the first semiconductor substrate, the first transistor facing the front-side of the first die; forming a second bond pad over the first front-side interconnect structure; and attaching a second front-side of a second die to the second bond pad of the first die, the second die comprising a second semiconductor substrate and a second transistor, the second transistor facing the front-side of the second die.

Abstract: A method for forming a semiconductor device is provided. The method includes applying a photoresist composition over a substrate, thereby forming a photoresist layer over the substrate; performing a first baking process to the photoresist layer; exposing the photoresist layer to an extreme ultraviolet (EUV) radiation, thereby forming a pattern therein; performing a second baking process to the photoresist layer; and developing the photoresist layer having the pattern therein using a developer, thereby forming a patterned photoresist layer. The first baking process and the second baking process are conducted under an ambient atmosphere having a humidity level ranging from 55% to 100%.

Abstract: In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

Abstract: A lithography method is described. The method includes forming a resist layer over a substrate, performing a treatment on the resist layer to form an upper portion of the resist layer having a first molecular weight and a lower portion of the resist layer having a second molecular weight less than the first molecular weight, performing an exposure process on the resist layer, and performing a developing process on the resist layer to form a patterned resist layer.

Abstract: In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

Abstract: A device includes a first transistor layer comprising a first gate electrode and a second transistor layer comprising a second gate electrode that is stacked with the first transistor layer. n intermetal structure comprising a conductive line is disposed between the first transistor layer and the second transistor layer. A first gate contact extends along a sidewall of the first gate electrode from a top surface of the first gate electrode to the conductive line 48G. A second gate contact extends along a sidewall of the second gate electrode from a top surface of the second gate electrode to the conductive line. The first gate electrode is electrically connected to the second gate electrode by the first gate contact, the second gate contact, and the conductive line.

Abstract: Examples described herein relate to multiple processor sockets comprising processors connected thereto and first circuitry. The first circuitry is to: based on a first mode of operation: configure the multiple processor sockets to operate with a single memory address space and share interfaces and based on a second mode of operation: configure the interfaces accessible to the multiple processor sockets to provide isolated communications to processor sockets in different partitions and configure the multiple processor sockets to operate in independent memory address spaces.

Abstract: A method of forming a semiconductor device includes forming a plurality of non-insulator structures on a substrate, the plurality of non-insulator structures being spaced apart by trenches, forming a sacrificial layer overfilling the trenches, reflowing the sacrificial layer at an elevated temperature, wherein a top surface of the sacrificial layer after the reflowing is lower than a top surface of the sacrificial layer before the reflowing, etching back the sacrificial layer to lower the top surface of the sacrificial layer to fall below top surfaces of the plurality of non-insulator structures, forming a dielectric layer on the sacrificial layer, and removing the sacrificial layer to form air gaps below the dielectric layer.

Abstract: In an example method, a user equipment (UE) determines a first identifier assigned to the UE for use on a first wireless communications network and one or more first time slots for monitoring the first wireless communication networks. The UE determines a second identifier assigned to the UE for use on a second wireless communications network and one or more second time slots for monitoring the second wireless communication networks. The UE determines that the one or more first time slots at least partially overlap the one or more second time slots, and in response, transmits to the second wireless communications network, a request for a third identifier to be assigned to the UE for use on the second wireless communications network and/or a request that the one or more second time slots be offset by an interval of time.

Abstract: A method for manufacturing a semiconductor device includes forming a photoresist layer including a photoresist composition over a substrate. The photoresist layer is selectively exposed to actinic radiation to form a latent pattern and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a patterned photoresist. The photoresist composition includes a photoactive compound and a resin comprising a radical-active functional group and an acid labile group.

Abstract: In an embodiment, a method includes performing a first atomic layer deposition (ALD) process to form a first material layer over a first blank wafer, the first ALD process comprising: performing a first precursor sub-cycle using a first precursor; performing a first purge sub-cycle using a inert gas; and performing a second precursor sub-cycle using a second precursor and the inert gas; and performing a second purge sub-cycle for a first duration over a second blank wafer different from the first blank wafer using the inert gas to deposit first defects onto the second blank wafer.

Abstract: A method of manufacturing a semiconductor device includes forming a first protective layer over an edge portion of a first main surface of a semiconductor substrate. A metal-containing photoresist layer is formed over the first main surface of the semiconductor substrate. The first protective layer is removed, and the metal-containing photoresist layer is selectively exposed to actinic radiation. A second protective layer is formed over the edge portion of the first main surface of the semiconductor substrate. The selectively exposed photoresist layer is developed to form a patterned photoresist layer, and the second protective layer is removed.

Abstract: A cleaning solution includes a solvent having Hansen solubility parameters: 25>?d>13, 25>?p>3, 30>?h>4; an acid having an acid dissociation constant pKa: ?11<pKa<4, or a base having pKa of 40>pKa>9.5; and a surfactant. The surfactant is an ionic or non-ionic surfactant, selected from R is substituted or unsubstituted aliphatic, alicyclic, or aromatic group, and non-ionic surfactant has A-X or A-X-A-X structure, where A is unsubstituted or substituted with oxygen or halogen, branched or unbranched, cyclic or non-cyclic, saturated C2-C100 aliphatic or aromatic group, X includes polar functional groups selected from —OH, ?O, —S—, —P—, —P(O2), —C(?O)SH, —C(?O)OH, —C(?O)OR—, —O—, —N—, —C(?O)NH, —SO2OH, —SO2SH, —SOH, —SO2—, —CO—, —CN—, —SO—, —CON—, —NH—, —SO3NH—, and SO2NH.