Patents by Inventor Ching Yu

Ching Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12174540
    Abstract: A method for manufacturing a semiconductor device includes forming a resist structure including forming a resist layer including a resist composition over a substrate. After forming the resist layer, the resist layer is treated with an additive. The additive is one or more selected from the group consisting of a radical inhibitor, a thermal radical initiator, and a photo radical initiator.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: December 24, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: An-Ren Zi, Ching-Yu Chang
  • Patent number: 12174170
    Abstract: A biochip packaging structure includes a chip packaging layer, a redistribution layer, and a microfluidic channel. The chip packaging layer includes a resin layer including a biochip and a conductive pillar located on each of two sides of the biochip. The biochip includes a first surface flush with and exposed out of a side of the resin layer. A first end of the conductive pillar is flush with a side of the resin layer opposite the biochip. A second end of the conductive pillar is flush with the first surface of the biochip. The redistribution layer includes a metal winding electrically coupled to the biochip and the adjacent conductive pillar. The metal winding includes a first winding portion coupled to the biochip and a second winding portion coupled between the first winding portion and the conductive pillar. The second winding portion is parallel to the first surface.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: December 24, 2024
    Assignee: Kore Semiconductor Co., Ltd.
    Inventors: Hsiang-Hua Lu, Ying-Chieh Pan, Ching-Yu Ni
  • Publication number: 20240420838
    Abstract: An embodiment of the invention provides a physiological information monitoring system. The physiological information monitoring system may include a server, a monitoring device and at least one gateway. The server may store and analyze physiological information of a user. The monitoring device may measure the physiological information and broadcast a Bluetooth Low Energy (BLE) advertising packet comprising the physiological information. The gateway may detect the BLE advertising packet and transmit the detected BLE advertising packet to the server.
    Type: Application
    Filed: November 24, 2023
    Publication date: December 19, 2024
    Inventors: Yen-Ching YU, Chi-Ming YANG, Jui-Wei CHIANG
  • Publication number: 20240419069
    Abstract: A method for forming a semiconductor device is provided. The method includes forming a photoresist layer comprising an organometallic compound over a substrate. The organometallic compound includes a metal core, at least one hydrolyzable ligand bonded to the metal core, and at least one photoacid generator ligand bonded to the metal core. The method further includes selectively exposing the photoresist layer to radiation and developing the photoresist layer to form a pattern in the photoresist layer.
    Type: Application
    Filed: June 15, 2023
    Publication date: December 19, 2024
    Inventors: An-Ren ZI, Yen-Yu KUO, Ching-Yu CHANG, Chin-Hsiang LIN
  • Publication number: 20240413149
    Abstract: An integrated circuit is provided which includes a first complementary field-effect transistor and a second complementary field-effect transistor. The first complementary field-effect transistor includes at least two first transistors respectively located on a first layer and a second layer. The second complementary field-effect transistor is disposed adjacent to the first complementary field-effect transistor. The second complementary field-effect transistor includes at least two second transistors respectively located on the first layer and the second layer. Type of one of the at least two first transistors located on the first layer is different from type of one of the at least two second transistors located on the first layer.
    Type: Application
    Filed: June 7, 2023
    Publication date: December 12, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ching-Yu HUANG, Wei-Cheng TZENG, Chun-Yen LIN, Shih-Wei PENG, Kuan Yu CHEN, Wei-Cheng LIN, Jiann-Tyng TZENG
  • Patent number: 12159787
    Abstract: In a pattern formation method, a photoresist layer is formed over a substrate by combining a first precursor and a second precursor in a vapor state to form a photoresist material. The first precursor is an organometallic having a formula MaRbXc, where M is one or more selected from the group consisting of Sn, Bi, Sb, In, and Te, R is an alkyl group that is substituted by different EDG and/or EWG, X is a halide or sulfonate group, and 1?a?2, b?1, c?1, and b+c?4. The second precursor is water, an amine, a borane, and/or a phosphine. The photoresist material is deposited over the substrate, and selectively exposed to actinic radiation to form a latent pattern, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: December 3, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Cheng Liu, Ming-Hui Weng, Jr-Hung Li, Yahru Cheng, Chi-Ming Yang, Tze-Liang Lee, Ching-Yu Chang
  • Publication number: 20240395539
    Abstract: A spin on composition includes a carbon backbone polymer; a first crosslinker; and a second crosslinker. The first crosslinker partially crosslinks the carbon backbone polymer at a temperature ranging from 100° C. to 170° C., and the second crosslinker crosslinks the carbon backbone polymer at a temperature ranging from 180° C. to 300° C. The second crosslinker is selected from the group consisting of A-(OH)x, A-(OR?)x, A-(C?C)x, and A-(C?C)x, where A is a monomer, oligomer, or a second polymer having a molecular weight ranging from 100 to 20,000, R? is an alkyloxy group, an alkenyl group, or an alkynyl group, and x ranges from 2 to 1000. The second crosslinker is different from the first crosslinker, and when either of the first crosslinker or the second crosslinker is a polymer, the polymer is a different polymer than the carbon backbone polymer.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing Hong HUANG, Ching-Yu CHANG, Wei-Han LAI
  • Publication number: 20240390438
    Abstract: The present disclosure provides a probiotics of PTA22 from rabbits, a nutritional composition for preparing food of rabbits and a composition for rabbits to degrade oxalic acid. Through this disclosure, the health of rabbits can be ensured and the resistance to pathogenic bacteria can be improved after rabbits consume the food containing PTA22. As well, the probiotic PTA22 can help rabbits reduce the risk of hypercalciuria and calculus.
    Type: Application
    Filed: August 12, 2024
    Publication date: November 28, 2024
    Inventors: JYH HORNG SHYU, LI YU CHIANG, YU HSIN CHANG, CHING YU CHIU, PEI-JU WANG
  • Publication number: 20240397431
    Abstract: A method for performing transmission power control of a wireless transceiver device in wireless communications system and associated apparatus are provided. The method may include: obtaining at least one indicator regarding a current channel, for channel detection of the current channel; detecting the current channel based on the at least one indicator to generate at least one channel detection result, wherein when one of the at least one channel detection result indicates a current channel model of the current channel, the current channel model is one of multiple predetermined channel models; and determining at least one transmission power value according to the at least one channel detection result, for performing packet transmission with the at least one transmission power value.
    Type: Application
    Filed: May 23, 2024
    Publication date: November 28, 2024
    Applicant: MEDIATEK INC.
    Inventors: I-Yin Yu, Kuan-Chih Kuo, Ching-Yu Kuo, Hao-Chih Yu, Wei-I Chiang
  • Patent number: 12156079
    Abstract: Devices, systems and methods for transitioning a UE to a new application server in response to a mobility event comprising, at a source application server handler: receiving an application ID (AC-ID) associated with an application client for a user equipment (UE); receiving a mobility event notification including a UE ID of the UE and a target data network access identifier (DNAI) to indicate a target edge data network to which a transition of a data connection for the application client is to be performed; encoding an outgoing transition request for transmission to a source application server to indicate the transition of the data connection from the source application server; and encoding an incoming transition request for transmission to a target application server handler (ASH) of the target edge data network to indicate the transition of the data connection to the target edge data network.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: November 26, 2024
    Assignee: Apple Inc.
    Inventors: Changhong Shan, Alexandre Saso Stojanovski, Ching-Yu Liao, Danny Moses
  • Patent number: 12154862
    Abstract: A method for manufacturing semiconductor devices include steps of depositing a first photoresist over a first dielectric layer, first exposing the first photoresist to a first light-exposure using a first lithographic mask, and second exposing the first photoresist to a second light-exposure using a second lithographic mask. An overlap region of the first photoresist is exposed to both the first light-exposure and the second light-exposure. The first dielectric layer is thereafter patterned to form a mask overlay alignment mark in the overlap region. The patterning includes etching the first dielectric layer form a trench, and filling the trench with a conductive material to produce the alignment mark. A second dielectric layer is deposited over the alignment mark, and a second photoresist is deposited over the second dielectric layer. A third lithographic mask is aligned to the second photoresist using the underlying mask overlay alignment mark for registration.
    Type: Grant
    Filed: May 2, 2023
    Date of Patent: November 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chia Hu, Chang-Ching Yu, Ming-Fa Chen
  • Publication number: 20240385514
    Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate, including combining a first precursor and a second precursor in a vapor state to form a photoresist material, and depositing the photoresist material over the substrate. A protective layer is formed over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation through the protective layer to form a latent pattern in the photoresist layer. The protective layer is removed, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hui WENG, Chen-Yu LIU, Chih-Cheng LIU, Yi-Chen KUO, Jia-Lin WEI, Yen-Yu CHEN, Jr-Hung LI, Yahru CHENG, Chi-Ming YANG, Tze-Liang LEE, Ching-Yu CHANG
  • Publication number: 20240387719
    Abstract: Various embodiments of the present disclosure are directed toward an integrated chip including an undoped layer overlying a substrate. A first barrier layer overlies the undoped layer. A doped layer overlies the first barrier layer. Further, a second barrier layer overlies the first barrier layer, where the second barrier layer is laterally offset from a perimeter of the doped layer by a non-zero distance. The first and second barrier layers comprise a same III-V semiconductor material. A first atomic percentage of a first element within the first barrier layer is less than a second atomic percentage of the first element within the second barrier layer.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 21, 2024
    Inventors: Yun-Hsiang Wang, Chun Lin Tsai, Jiun-Lei Jerry Yu, Po-Chih Chen, Chia-Ling Yeh, Ching Yu Chen
  • Publication number: 20240385523
    Abstract: Method of manufacturing semiconductor device includes forming photoresist layer over substrate. Forming photoresist layer includes combining first precursor and second precursor in vapor state to form photoresist material, wherein first precursor is organometallic having formula: MaRbXc, where M at least one of Sn, Bi, Sb, In, Te, Ti, Zr, Hf, V, Co, Mo, W, Al, Ga, Si, Ge, P, As, Y, La, Ce, Lu; R is substituted or unsubstituted alkyl, alkenyl, carboxylate group; X is halide or sulfonate group; and 1?a?2, b?1, c?1, and b+c?5. Second precursor is at least one of an amine, a borane, a phosphine. Forming photoresist layer includes depositing photoresist material over the substrate. The photoresist layer is selectively exposed to actinic radiation to form latent pattern, and the latent pattern is developed by applying developer to selectively exposed photoresist layer to form pattern.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Cheng LIU, Yi-Chen KUO, Jia-Lin WEI, Ming-Hui WENG, Yen-Yu CHEN, Jr-Hung LI, Yahru CHENG, Chi-Ming YANG, Tze-Liang LEE, Ching-Yu CHANG
  • Publication number: 20240387189
    Abstract: A method includes forming a dielectric layer over a substrate; forming a patterned amorphous silicon layer over a dielectric layer; depositing a first spacer layer over the patterned amorphous silicon layer; depositing a second spacer layer over the first spacer layer; forming a photoresist having an opening over the substrate; depositing a hard mask layer in the opening of the photoresist; after depositing the hard mask layer in the opening of the photoresist, removing the photoresist; and performing an etching process to etch the dielectric layer by using the patterned amorphous silicon layer, the first spacer layer, the second spacer layer, and the hard mask layer as an etch mask, in which the etching process etches the second spacer layer at a slower etch rate than etching the first spacer layer.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ching-Yu CHANG, Jei-Ming CHEN, Tze-Liang LEE
  • Publication number: 20240387359
    Abstract: Semiconductor packages and methods of forming the same are disclosed. An semiconductor package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.
    Type: Application
    Filed: July 28, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Yu Huang, Han-Ping Pu, Ming-Kai Liu, Ting-Chu Ko, Yung-Ping Chiang, Chang-Wen Huang, Yu-Sheng Hsieh
  • Publication number: 20240387729
    Abstract: A method includes etching a first portion and a second portion of a dummy gate stack to form a first opening and a second opening, respectively, and depositing a silicon nitride layer to fill the first opening and the second opening. The deposition of the silicon nitride layer comprises a first process selected from treating the silicon nitride layer using hydrogen radicals, implanting the silicon nitride layer, and combinations thereof. The method further includes etching a third portion of the dummy gate stack to form a trench, etching a semiconductor fin underlying the third portion to extend the trench down into a bulk portion of a semiconductor substrate underlying the dummy gate stack, and depositing a second silicon nitride layer into the trench.
    Type: Application
    Filed: July 17, 2024
    Publication date: November 21, 2024
    Inventors: Chung-Ting Ko, Han-Chi Lin, Chunyao Wang, Ching Yu Huang, Tze-Liang Lee, Yung-Chih Wang
  • Publication number: 20240387173
    Abstract: In a pattern formation method, a photoresist layer is formed over a substrate by combining a first precursor and a second precursor in a vapor state to form a photoresist material. The first precursor is an organometallic having a formula MaRbXc, where M is one or more selected from the group consisting of Sn, Bi, Sb, In, and Te, R is an alkyl group that is substituted by different EDG and/or EWG, X is a halide or sulfonate group, and 1?a?2, b?1, c?1, and b+c?4. The second precursor is water, an amine, a borane, and/or a phosphine. The photoresist material is deposited over the substrate, and selectively exposed to actinic radiation to form a latent pattern, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Cheng LIU, Ming-Hui WENG, Jr-Hung LI, Yahru CHENG, Chi-Ming YANG, Tze-Liang LEE, Ching-Yu CHANG
  • Publication number: 20240387454
    Abstract: A memory device including a first semiconductor die and a memory cube mounted on and connected with the first semiconductor die is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes second semiconductor dies laterally wrapped by an encapsulant and a redistribution structure disposed on the second semiconductor dies and the encapsulant. The second semiconductor dies of the multiple stacked tiers are electrically connected with the first semiconductor die through the redistribution structures in the multiple stacked tiers.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Yu Huang, Han-Ping Pu, Ming-Kai Liu, Ting-Chu Ko, Yung-Ping Chiang, Chang-Wen Huang, Yu-Sheng Hsieh
  • Patent number: 12148610
    Abstract: A composition, comprising: a carbon backbone polymer; a first crosslinker; and a second crosslinker. The first crosslinker partially crosslinks the carbon backbone polymer at a temperature ranging from 100° C. to 170° C., and the second crosslinker crosslinks the carbon backbone polymer at a temperature ranging from 180° C. to 300° C. The first crosslinker is one or more selected from the group consisting of A-(OR)x, A-(NR)x, where A is a monomer, oligomer, or a second polymer having a molecular weight ranging from 100 to 20,000, R is an alkyl group, cycloalkyl group, cycloalkylepoxy group, or C3-C15 heterocyclic group, OR is an alkyloxy group, cycloalkyloxy group, carbonate group, alkylcarbonate group, alkyl carboxylate group, tosylate group, or mesylate group, NR is an alkylamide group or an alkylamino group, and x ranges from 2 to 1000. The second crosslinker is different from the first crosslinker.
    Type: Grant
    Filed: June 29, 2023
    Date of Patent: November 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jing Hong Huang, Ching-Yu Chang, Wei-Han Lai