Patents by Inventor Ching Yu

Ching Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • PHOTORESIST MATERIALS AND ASSOCIATED METHODS
    Publication number: 20220365428
    Abstract: Photoresist materials described herein may include various types of tin (Sn) clusters having one or more types of ligands. As an example, a photoresist material described herein may include tin clusters bearing two or more different types of carboxylate ligands. As another example, a photoresist material described herein may include tin oxide clusters that include carbonate ligands. The two or more different types of carboxylate ligands and the carbonate ligands may reduce, minimize, and/or prevent crystallization of the photoresist materials described herein, which may increase the coating performance of the photoresist materials and may decrease the surface roughness of photoresist layers formed using the photoresist materials described herein.
    Type: Application
    Filed: May 14, 2021
    Publication date: November 17, 2022
    Inventors: Ming-Hui WENG, Yahru CHENG, Ching-Yu CHANG
  • METHOD AND APPARATUS OF PATTERNING A SEMICONDUCTOR DEVICE
    Publication number: 20220365437
    Abstract: A method of forming a masking element is provided. The method includes forming a photoresist material having a polymer backbone over a substrate, where the polymer backbone includes a linking group that links a first polymer segment to a second polymer segment, each of the first and the second polymer segments having an ultraviolet (UV) curable group. The method includes exposing the photoresist material under a first UV radiation to break the link between the first polymer segment and the second polymer segment. The method includes exposing the photoresist material under a second UV radiation different from the first UV radiation to form a patterned resist layer. And the method includes developing the patterned resist layer to form a masking element.
    Type: Application
    Filed: July 28, 2022
    Publication date: November 17, 2022
    Inventors: An-Ren Zi, Ching-Yu Chang
  • SPIN ON CARBON COMPOSITION AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
    Publication number: 20220367178
    Abstract: A spin on carbon composition, comprises: a carbon backbone polymer; a first crosslinker; and a second crosslinker. The first crosslinker reacts with the carbon backbone polymer to partially crosslink the carbon backbone polymer at a first temperature, and the second crosslinker reacts with the carbon backbone polymer to further crosslink the carbon backbone polymer at a second temperature higher than the first temperature. The first crosslinker is a monomer, oligomer, or polymer. The second crosslinker is a monomer, oligomer, or polymer. The first and second crosslinkers are different from each other. When either of the first crosslinker or the second crosslinker is a polymer, the polymer is a different polymer than the carbon backbone polymer.
    Type: Application
    Filed: July 13, 2022
    Publication date: November 17, 2022
    Inventors: Jing Hong HUANG, Ching-Yu CHANG, Wei-Han LAI
  • Methods of Determining Process Recipes and Forming a Semiconductor Device
    Publication number: 20220367293
    Abstract: In an embodiment, a method includes performing a first atomic layer deposition (ALD) process to form a first material layer over a first blank wafer, the first ALD process comprising: performing a first precursor sub-cycle using a first precursor; performing a first purge sub-cycle using a inert gas; and performing a second precursor sub-cycle using a second precursor and the inert gas; and performing a second purge sub-cycle for a first duration over a second blank wafer different from the first blank wafer using the inert gas to deposit first defects onto the second blank wafer.
    Type: Application
    Filed: October 4, 2021
    Publication date: November 17, 2022
    Inventors: Jung-Hau Shiu, Ching-Yu Chang, Jei Ming Chen, Jr-Yu Chen, Tze-Liang Lee
  • NEGATIVE TONE PHOTORESIST FOR EUV LITHOGRAPHY
    Publication number: 20220365430
    Abstract: A negative tone photoresist and method for developing the negative tone photoresist is disclosed. For example, the negative tone photoresist includes a solvent, a dissolution inhibitor, and a polymer. The polymer includes a hydroxyl group. The polymer may be greater than 40 weight percent of a total weight of the negative tone photoresist.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 17, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Po YANG, Wei-Han LAI, Ching-Yu CHANG
  • PHOTORESIST COMPOSITION AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE
    Publication number: 20220365427
    Abstract: A method for manufacturing a semiconductor device includes forming a resist layer including a resist composition over a substrate. The resist composition includes: a metal, a ligand, and a solvent. The solvent is mixture of a first solvent having a vapor pressure of at least 0.75 kPa, wherein the first solvent is one or more of an ether, an ester, an alkane, an aldehyde, or a ketone, and a second solvent different from the first solvent. Alternatively, the solvent is a third solvent, wherein the third solvent is a C4-C14 tertiary alcohol. The resist layer is patterned.
    Type: Application
    Filed: April 30, 2021
    Publication date: November 17, 2022
    Inventors: An-Ren ZI, Ching-Yu CHANG
  • Stress modulation for dielectric layers
    Patent number: 11502196
    Abstract: A method includes etching a first portion and a second portion of a dummy gate stack to form a first opening and a second opening, respectively, and depositing a silicon nitride layer to fill the first opening and the second opening. The deposition of the silicon nitride layer comprises a first process selected from treating the silicon nitride layer using hydrogen radicals, implanting the silicon nitride layer, and combinations thereof. The method further includes etching a third portion of the dummy gate stack to form a trench, etching a semiconductor fin underlying the third portion to extend the trench down into a bulk portion of a semiconductor substrate underlying the dummy gate stack, and depositing a second silicon nitride layer into the trench.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: November 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Ting Ko, Han-Chi Lin, Chunyao Wang, Ching Yu Huang, Tze-Liang Lee, Yung-Chih Wang
  • SEMICONDUCTOR DEVICE
    Publication number: 20220359275
    Abstract: A semiconductor device includes a plurality of gate electrodes over a substrate, and a source/drain epitaxial layer. The source/drain epitaxial layer is disposed in the substrate and between two adjacent gate electrodes, wherein a bottom surface of the source/drain epitaxial layer is buried in the substrate to a depth less than or equal to two-thirds of a spacing between the two adjacent gate electrodes.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 10, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang, Chung-Hao Chu, Ching-Yu Yang
  • METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
    Publication number: 20220359190
    Abstract: Method of manufacturing a semiconductor device, includes forming a protective layer over substrate having a plurality of protrusions and recesses. The protective layer includes polymer composition including polymer having repeating units of one or more of: Wherein a, b, c, d, e, f, g, h, and i are each independently H, —OH, —ROH, —R(OH)2, —NH2, —NHR, —NR2, —SH, —RSH, or —R(SH)2, wherein at least one of a, b, c, d, e, f, g, h, and i on each repeating unit is not H. R, R1, and R2 are each independently a C1-C10 alkyl group, a C3-C10 cycloalkyl group, a C1-C10 hydroxyalkyl group, a C2-C10 alkoxy group, a C2-C10 alkoxy alkyl group, a C2-C10 acetyl group, a C3-C10 acetylalkyl group, a C1-C10 carboxyl group, a C2-C10 alkyl carboxyl group, or a C4-C10 cycloalkyl carboxyl group, and n is 2-1000. A resist layer is formed over the protective layer, and the resist layer is patterned.
    Type: Application
    Filed: April 23, 2021
    Publication date: November 10, 2022
    Inventors: Jing Hong Huang, Wei-Han Lai, Ching-Yu Chang
  • FINFET DEVICE AND METHOD
    Publication number: 20220359735
    Abstract: A method includes forming a fin on a substrate, forming an insulating material over the fin, recessing the insulating material to form an isolation region surrounding the fin, wherein an upper portion of the fin protrudes above the isolation region, performing a trimming process to reduce a width of the upper portion of the fin, and forming a gate structure extending over the isolation region and the upper portion of the fin.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 10, 2022
    Inventors: Chung-Shu Wu, Ying-Ya Hsu, Ching-Yu Pan, Hsiu-Hao Tsao, An Chyi Wei, Yuan-Hung Chiu
  • Method for forming semiconductor structure by patterning resist layer having inorganic material
    Patent number: 11495460
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a material layer over a substrate, and forming a first layer over the material layer. The method also includes forming a second layer over the first layer, and the second layer includes an auxiliary. The method further includes forming a third layer over the second layer, and the third layer includes an inorganic material, the inorganic material includes a plurality of metallic cores, and a plurality of first linkers bonded to the metallic cores. A topmost surface of the second layer is in direct contact with a bottommost surface of the third layer. The method includes exposing a portion of the second layer by performing an exposure process, and the auxiliary reacts with the first linkers during the exposure process.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: November 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: An-Ren Zi, Chin-Hsiang Lin, Ching-Yu Chang
  • Signal control module and low coherence interferometry
    Patent number: 11496677
    Abstract: A signal control module integrated to a low coherence interferometry including a one-dimensional (1D) array image sensor is provided. The signal control module includes an image acquisition controller and a signal controller. The image acquisition controller sends a 1D image acquisition control signal. The signal controller sends a two-dimensional (2D) image acquisition control signal, wherein the 1D and 2D image acquisition control signals are synchronized with each other. The 1D array image sensor captures 1D image information of an object-to-be-tested at different positions along a direction according to the 1D and 2D image acquisition control signals. The 1D image information constitutes 2D image information. Furthermore, a low coherence interferometry is provided.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: November 8, 2022
    Assignee: National Taiwan University
    Inventors: Hsiang-Chieh Lee, Ting-Hao Chen, Ting-Yen Tsai, Chuan-Bor Chueh, Yu-Wei Chang, Ching-Yu Wang
  • METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
    Publication number: 20220351964
    Abstract: A method of manufacturing a semiconductor device includes forming a dopant layer including a dopant composition over a substrate. A resist layer including a resist composition is formed over the dopant layer. A dopant is diffused from the dopant composition in the dopant layer into the resist layer; and a pattern is formed in the resist layer.
    Type: Application
    Filed: April 30, 2021
    Publication date: November 3, 2022
    Inventors: An-Ren ZI, Ching-Yu CHANG
  • CLEANING SOLUTION AND METHOD OF CLEANING WAFER
    Publication number: 20220351963
    Abstract: A cleaning solution includes a solvent having Hansen solubility parameters: 25>?d>13, 25>?p>3, 30>?h>4; an acid having an acid dissociation constant pKa: ?11<pKa<4, or a base having pKa of 40>pKa>9.5; and a surfactant. The surfactant is an ionic or non-ionic surfactant, selected from R is substituted or unsubstituted aliphatic, alicyclic, or aromatic group, and non-ionic surfactant has A-X or A-X-A-X structure, where A is unsubstituted or substituted with oxygen or halogen, branched or unbranched, cyclic or non-cyclic, saturated C2-C100 aliphatic or aromatic group, X includes polar functional groups selected from —OH, ?O, —S—, —P—, —P(O2), —C(?O)SH, —C(?O)OH, —C(?O)OR—, —O—, —N—, —C(?O)NH, —SO2OH, —SO2SH, —SOH, —SO2—, —CO—, —CN—, —SO—, —CON—, —NH—, —SO3NH—, and SO2NH.
    Type: Application
    Filed: June 29, 2022
    Publication date: November 3, 2022
    Inventors: An-Ren ZI, Ching-Yu CHANG
  • System, method and associated computer readable medium for designing integrated circuit with pre-layout RC information
    Patent number: 11487924
    Abstract: A system for designing an integrated circuit having pre-layout RC information is disclosed. The system includes: at least one processor; and at least one memory including computer program code for one or more programs, the at least one memory and the computer program code configured to, with the at least one processor, cause the system to: generate current and voltage information for a schematic having device array layout constraint included; create interconnection topology patterns and realizing route for the schematic; generate RC information according to the route; and determine if the schematic having the device array layout constraint and the RC information included violates one or more of the system design rule constraints. An associated method and a computer readable medium are also disclosed.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: November 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chin-Sheng Chen, Ching-Yu Chai, Wei-Yi Hu
  • Method Of Fabricating Semiconductor Device With Reduced Trench Distortions
    Publication number: 20220344170
    Abstract: A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.
    Type: Application
    Filed: July 11, 2022
    Publication date: October 27, 2022
    Inventors: Yung-Sung Yen, Chung-Ju Lee, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu, Kuei-Shun Chen, Ru-Gun Liu, Shau-Lin Shue, Tsai-Sheng Gau, Yung-Hsu Wu
  • FAN-OUT PACKAGING STRUCTURE
    Publication number: 20220344277
    Abstract: A fan-out packaging structure includes a redistribution layer and a positioning sheet formed on the redistribution layer. The positioning sheet defines at least one opening penetrating opposite sides of the positioning sheet. At least one chip is mounted in the at least one opening. The redistribution layer comprises at least one conductive circuit. The at least one chip is electrically coupled to a corresponding one conductive circuit.
    Type: Application
    Filed: July 8, 2022
    Publication date: October 27, 2022
    Inventors: YING-CHIEH PAN, HSIANG-HUA LU, CHING-YU NI
  • Semiconductor device and method
    Patent number: 11482411
    Abstract: A method of forming a semiconductor device includes forming a mask layer over a substrate and forming an opening in the mask layer. A gap-filling material is deposited in the opening. A plasma treatment is performed on the gap-filling material. The height of the gap-filling material is reduced. The mask layer is removed. The substrate is patterned using the gap-filling material as a mask.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: October 25, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ching-Yu Chang, Jei Ming Chen, Tze-Liang Lee
  • PHOTORESIST TOP COATING MATERIAL FOR ETCHING RATE CONTROL
    Publication number: 20220334482
    Abstract: A patterning stack is provided. The patterning stack includes a bottom anti-reflective coating (BARC) layer over a substrate, a photoresist layer having a first etching resistance over the BARC layer, and a top coating layer having a second etching resistance greater than the first etching resistance over the photoresist layer. The top coating layer includes a polymer having a polymer backbone including at least one functional unit of high etching resistance and one or more acid labile groups attached to the polymer backbone or a silicon cage compound.
    Type: Application
    Filed: April 15, 2021
    Publication date: October 20, 2022
    Inventors: Tzu-Yang LIN, Ching-Yu CHANG, Chin-Hsiang LIN
  • Forming Low-Stress Silicon Nitride Layer Through Hydrogen Treatment
    Publication number: 20220336202
    Abstract: A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 20, 2022
    Inventors: Wei-Che Hsieh, Ching Yu Huang, Hsin-Hao Yeh, Chunyao Wang, Tze-Liang Lee