Patents by Inventor Ching Yu

Ching Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11476108
    Abstract: A method of manufacturing a semiconductor device includes forming a spin on carbon layer comprising a spin on carbon composition over a semiconductor substrate. The spin on carbon layer is first heated at a first temperature to partially crosslink the spin on carbon layer. The spin on carbon layer is second heated at a second temperature to further crosslink the spin on carbon layer. An overlayer is formed over the spin on carbon layer. The second temperature is higher than the first temperature.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: October 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jing Hong Huang, Ching-Yu Chang, Wei-Han Lai
  • Patent number: 11468003
    Abstract: A processor includes a scalar processor core and a vector coprocessor core coupled to the scalar processor core. The scalar processor core is configured to retrieve an instruction stream from program storage, and pass vector instructions in the instruction stream to the vector coprocessor core. The vector coprocessor core includes a register file, a plurality of execution units, and a table lookup unit. The register file includes a plurality of registers. The execution units are arranged in parallel to process a plurality of data values. The execution units are coupled to the register file. The table lookup unit is coupled to the register file in parallel with the execution units. The table lookup unit is configured to retrieve table values from one or more lookup tables stored in memory by executing table lookup vector instructions in a table lookup loop.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: October 11, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: Ching-Yu Hung, Shinri Inamori, Jagadeesh Sankaran, Peter Chang
  • Publication number: 20220319862
    Abstract: A method includes forming a dielectric layer over a substrate; forming a patterned amorphous silicon layer over a dielectric layer; depositing a first spacer layer over the patterned amorphous silicon layer; depositing a second spacer layer over the first spacer layer; forming a photoresist having an opening over the substrate; depositing a hard mask layer in the opening of the photoresist; after depositing the hard mask layer in the opening of the photoresist, removing the photoresist; and performing an etching process to etch the dielectric layer by using the patterned amorphous silicon layer, the first spacer layer, the second spacer layer, and the hard mask layer as an etch mask, in which the etching process etches the second spacer layer at a slower etch rate than etching the first spacer layer.
    Type: Application
    Filed: August 2, 2021
    Publication date: October 6, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ching-Yu CHANG, Jei-Ming CHEN, Tze-Liang LEE
  • Patent number: 11462481
    Abstract: A fan-out packaging structure includes a redistribution layer and a positioning sheet formed on the redistribution layer. The positioning sheet defines at least one opening penetrating opposite sides of the positioning sheet. At least one chip is mounted in the at least one opening. The redistribution layer comprises at least one conductive circuit. The at least one chip is electrically coupled to a corresponding one conductive circuit.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: October 4, 2022
    Assignee: Kore Semiconductor Co., Ltd.
    Inventors: Ying-Chieh Pan, Hsiang-Hua Lu, Ching-Yu Ni
  • Patent number: 11460776
    Abstract: A method of making a semiconductor device is provided. The method includes forming a photoresist material over a substrate, the photoresist material having a polymer that includes a backbone having a segment and a linking group, the segment including a carbon chain and an ultraviolet (UV) curable group, the UV curable group coupled to the carbon chain and to the linking group; performing a first exposure process that breaks the backbone of the polymer via decoupling the linking group from the connected UV curable group of each segment; performing a second exposure process to form a patterned photoresist layer; and developing the patterned photoresist layer.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: October 4, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: An-Ren Zi, Ching-Yu Chang
  • Patent number: 11461085
    Abstract: A multiple storage node system including a first and second node is provided. The first node includes a first baseboard management controller (BMC), a first flash ROM configured to store a first flash image, and a first switch device configured to connect the first BMC to the first flash ROM. The second node includes an exact configuration of the first node. The first BMC is connected to the second switch device, and the second flash image is the same as the first flash.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: October 4, 2022
    Assignee: QUANTA COMPUTER INC.
    Inventors: Kai-Yeh Pan, Chun-Ching Yu, Shuen-Hung Wang
  • Publication number: 20220308452
    Abstract: In a method, a resist material is dispensed through a tube of a nozzle of a resist pump system on a wafer. The tube extends from a top to a bottom of the nozzle and has upper, lower, and middle segments. When not dispensing, the resist material is retracted from the lower and the middle segments, and maintained in the upper segment of the tube. When retracting, a first solvent is flown through a tip of the nozzle at the bottom of the nozzle to fill the lower segment of the tube with the first solvent and to produce a gap in the middle segment of the tube between the resist material and the first solvent. The middle segment includes resist material residues on an inner surface wall of the tube and vapor of the first solvent. The vapor of the first solvent prevents the resist material residues from drying.
    Type: Application
    Filed: March 26, 2021
    Publication date: September 29, 2022
    Inventors: Ya-Ching CHANG, Chen-Yu LIU, Ching-Yu CHANG, Chin-Hsiang LIN
  • Patent number: 11456170
    Abstract: A cleaning solution includes a first solvent having Hansen solubility parameters 25>?d>13, 25>?p>3, and 30>?h>4; an acid having an acid dissociation constant, pKa, of ?11<pKa<4, or a base having a pKa of 40 > pKa>9.5; and a surfactant. The surfactant is one or more of an ionic surfactant, a polyethylene oxide and a polypropylene oxide, a non-ionic surfactant, and combinations thereof.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: September 27, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: An-Ren Zi, Ching-Yu Chang
  • Patent number: 11456266
    Abstract: A method of manufacturing a bump structure includes forming a passivation layer over a substrate. A metal pad structure is formed over the substrate, wherein the passivation layer surrounds the metal pad structure. A polyimide layer including a polyimide is formed over the passivation layer and the metal pad structure. A metal bump is formed over the metal pad structure and the polyimide layer. The polyimide is a reaction product of a dianhydride and a diamine, wherein at least one of the dianhydride and the diamine comprises one selected from the group consisting of a cycloalkane, a fused ring, a bicycloalkane, a tricycloalkane, a bicycloalkene, a tricycloalkene, a spiroalkane, and a heterocyclic ring.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: September 27, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ching-Yu Chang, Ming-Da Cheng, Ming-Hui Weng
  • Publication number: 20220301822
    Abstract: An embodiment is an apparatus, such as a plasma chamber. The apparatus includes chamber walls and a chamber window defining an enclosed space. A chamber window is disposed between a plasma antenna and a substrate support. A gas delivery source is mechanically coupled to the chamber window. The gas delivery source comprises a gas injector having a passageway, a window at a first end of the passageway, and a nozzle at a second end of the passageway. The nozzle of the gas delivery source is disposed in the enclosed space. A fastening device is mechanically coupled to the gas delivery source. The fastening device is adjustable to adjust a sealing force against the gas injector.
    Type: Application
    Filed: June 6, 2022
    Publication date: September 22, 2022
    Inventors: Yung-Shun HSU, Ching-Yu CHANG, Chiao-Kai CHANG, Wai Hong CHEAH, Chien-Fang LIN
  • Publication number: 20220299879
    Abstract: A lithography method is described. The method includes forming a resist layer over a substrate, performing a treatment on the resist layer to form an upper portion of the resist layer having a first molecular weight and a lower portion of the resist layer having a second molecular weight less than the first molecular weight, performing an exposure process on the resist layer, and performing a developing process on the resist layer to form a patterned resist layer.
    Type: Application
    Filed: March 18, 2021
    Publication date: September 22, 2022
    Inventors: Ming-Hui WENG, Ching-Yu CHANG
  • Patent number: 11452001
    Abstract: Systems and methods are provided for efficient group-based handling of massive internet of things (M-IoT) devices that are compatible with both current cellular networks, and next generation 5G systems. Examples allow reduced overhead between a (radio) access network (R)AN and a core network (CN) that originates from unnecessary signaling traffic for IoT devices transitioning from IDLE to CONNECTED mode, especially when sending small data packets. In addition, or in other embodiments, mobility solutions are provided for group based M-IoT.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: September 20, 2022
    Assignee: APPLE INC.
    Inventors: Ching-Yu Liao, Xiruo Liu, Liuyang Yang, Moreno Ambrosin
  • Publication number: 20220291586
    Abstract: A method for manufacturing a semiconductor device includes forming a resist underlayer over a substrate. The resist underlayer includes an underlayer composition, including: a polymer with pendant photoacid generator (PAG) groups, pendant thermal acid generator (TAG) groups, a combination of pendant PAG and pendant TAG groups, pendant photobase generator (PBG) groups, pendant thermal base generator (TBG) groups, or a combination of pendant PBG and pendant TBG groups. A photoresist layer including a photoresist composition is formed over the resist underlayer. The photoresist layer is selectively exposed to actinic radiation. The selectively exposed photoresist layer is developed to form a pattern in the photoresist layer.
    Type: Application
    Filed: September 27, 2021
    Publication date: September 15, 2022
    Inventors: Ming-Hui WENG, Chen-Yu LIU, Ching-Yu CHANG
  • Publication number: 20220291587
    Abstract: A method for manufacturing a semiconductor device includes forming a resist structure including forming a resist layer including a resist composition over a substrate. After forming the resist layer, the resist layer is treated with an additive. The additive is one or more selected from the group consisting of a radical inhibitor, a thermal radical initiator, and a photo radical initiator.
    Type: Application
    Filed: September 22, 2021
    Publication date: September 15, 2022
    Inventors: An-Ren Zi, Ching-Yu Chang
  • Patent number: 11442364
    Abstract: A method includes forming a bottom layer over a semiconductor substrate, where the bottom layer includes a polymer bonded to a first cross-linker and a second cross-linker, the first cross-linker being configured to be activated by ultraviolet (UV) radiation and the second cross-linker being configured to be activated by heat at a first temperature. The method then proceeds to exposing the bottom layer to a UV source to activate the first cross-linker, resulting in an exposed bottom layer, where the exposing activates the first cross-linker. The method further includes baking the exposed bottom layer, where the baking activates the second cross-linker.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: September 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jing Hong Huang, Chien-Wei Wang, Shang-Wern Chang, Ching-Yu Chang
  • Patent number: 11443980
    Abstract: A method of fabricating a semiconductor device includes at least the following steps is provided. A first metal layer is formed on a substrate. A first dielectric layer is formed on the substrate. The first dielectric layer is patterned, thereby forming a first opening exposing the first metal layer. A second metal layer is formed on the first dielectric layer and filling into the first opening. The second metal layer is patterned, thereby forming a metal pad. A second dielectric layer is formed on the first dielectric layer and the metal pad. The second dielectric layer is patterned, thereby forming a second opening exposing the metal pad. A first annealing process is performed in an atmosphere of a gas including 50 vol % to 100 vol % of hydrogen.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: September 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang, Chung-Hao Chu, Ching-Yu Yang
  • Patent number: 11437498
    Abstract: A method includes forming a fin on a substrate, forming an insulating material over the fin, recessing the insulating material to form an isolation region surrounding the fin, wherein an upper portion of the fin protrudes above the isolation region, performing a trimming process to reduce a width of the upper portion of the fin, and forming a gate structure extending over the isolation region and the upper portion of the fin.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: September 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Shu Wu, Ying-Ya Hsu, Ching-Yu Pan, Hsiu-Hao Tsao, An Chyi Wei, Yuan-Hung Chiu
  • Publication number: 20220260918
    Abstract: In a pattern formation method, a bottom layer is formed over an underlying layer. A middle layer is formed over the bottom layer. A resist pattern is formed over the middle layer. The middle layer is patterned by using the resist pattern as an etching mask. The bottom layer is patterned by using the patterned middle layer. The underlying layer is patterned. The middle layer contains silicon in an amount of 50 wt % or more and an organic material. In one or more of the foregoing and following embodiments, an annealing operation is further performed after the middle layer is formed.
    Type: Application
    Filed: May 2, 2022
    Publication date: August 18, 2022
    Inventors: Chien-Wei WANG, Ching-Yu CHANG, Shang-Wern CHANG, Yen-Hao CHEN
  • Patent number: 11408692
    Abstract: A liquid cooling device includes a liquid cooling conductor, a detecting probe, and a determining circuit. The liquid cooling conductor includes a chamber defined therein for communicating with the outside, the chamber is configured to accommodate the coolant, and the surface of the liquid cooling conductor is provided with at least one communicating port communicating with the chamber; wherein the liquid cooling conductor is formed joining at least two combination blocks, and at least one of the two combination blocks is a metal conductor. The detecting probe is disposed on the liquid cooling conductor and normally electrically disconnected from the metal conductor. The determining circuit is electrically connected to the metal conductor and the detecting probe, and generates a liquid leakage alarm signal when the metal conductor and the detecting probe are electrically connected.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: August 9, 2022
    Assignee: GIGA-BYTE TECHNOLOGY CO., LTD.
    Inventors: Shun-Chih Huang, Tai-Chuan Mao, Ching-Yu Lu, Yi-Jhen Lin, Liang-Yu Wu
  • Patent number: 11411108
    Abstract: A semiconductor device includes a gate stack over a semiconductor substrate. A spacer extends along a first sidewall of the gate stack. An epitaxy structure is in the semiconductor substrate. A liner wraps around the epitaxy structure and has an outer surface in contact with the semiconductor substrate and an inner surface facing the epitaxy structure. The outer surface of the liner has a first facet extending upwards and towards the gate stack from a bottom of the first liner and a second facet extending upwards and towards an outer sidewall of the spacer from a top of the first facet to a top of the liner, such that a corner is formed between the first facet and the second facet, and the inner surface of the first liner defines a first curved corner pointing towards the corner formed between the first facet and the second facet.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Fen Chen, Chui-Ya Peng, Ching Yu, Pin-Hen Lin, Yen Chuang, Yuh-Ta Fan