Abstract: An operation method of a software program meeting UEFI specifications for configuring a GPIO port is provided. The operation method includes: operating in a command-line mode to display, on a display device, a first prompt for guiding a user to input a string of command-line arguments; in response to receipt of a string of command-line arguments for reading content stored in a register that corresponds to one of GPIO pins of the GPIO port under the command-line mode, displaying, on the display device, a default value of the register that corresponds to a function of said one of the GPIO pins; and in response to receipt of a string of command-line arguments for setting a register that corresponds to one of the GPIO pins to a set value under the command-line mode, writing the set value to the register to replace a current value with the set value.

Abstract: A method for returning to a basic input/output system (BIOS) setup utility while in a shell environment during a booting process of a computing system includes: upon execution of an update Unified Extensible Firmware Interface (UEFI) (BIOS) firmware file, storing a dynamic command in a command storage; storing a back protocol in the storage module, the back protocol being linked to a back function that, when executed, causes the CPU to call a program file that, when executed by the CPU, causes the CPU to enter a BIOS setup utility, the dynamic command being linked to accessing a memory location in which the back protocol is stored; and in response to receipt of the dynamic command while in the shell environment, locating the back protocol, performing the back function and calling the specific program file, which causes the CPU to enter the BIOS setup utility.

Abstract: A method for returning to a basic input/output system (BIOS) setup utility while in a shell environment during a booting process of a computing system includes: upon execution of an update Unified Extensible Firmware Interface (UEFI) (BIOS) firmware file, storing a dynamic command in a command storage; storing a back protocol in the storage module, the back protocol being linked to a back function that, when executed, causes the CPU to call a program file that, when executed by the CPU, causes the CPU to enter a BIOS setup utility, the dynamic command being linked to accessing a memory location in which the back protocol is stored; and in response to receipt of the dynamic command while in the shell environment, locating the back protocol, performing the back function and calling the specific program file, which causes the CPU to enter the BIOS setup utility.

Abstract: An operation method of a software program meeting UEFI specifications for configuring a GPIO port is provided. The operation method includes: operating in a command-line mode to display, on a display device, a first prompt for guiding a user to input a string of command-line arguments; in response to receipt of a string of command-line arguments for reading content stored in a register that corresponds to one of GPIO pins of the GPIO port under the command-line mode, displaying, on the display device, a default value of the register that corresponds to a function of said one of the GPIO pins; and in response to receipt of a string of command-line arguments for setting a register that corresponds to one of the GPIO pins to a set value under the command-line mode, writing the set value to the register to replace a current value with the set value.

Abstract: The present invention provides methods for treating cancer, by administering a therapeutically effective amount of a compound of formula (I), or a pharmaceutically acceptable salt thereof. Also provided are methods for reducing cancer cell metastasis, by administering a therapeutically effective amount of a compound of formula (I) described herein or a pharmaceutically acceptable salt thereof.

Abstract: The present invention provides methods for treating cancer, by administering a therapeutically effective amount of a compound of formula (I), or a pharmaceutically acceptable salt thereof. Also provided are methods for reducing cancer cell metastasis, by administering a therapeutically effective amount of a compound of formula (I) described herein or a pharmaceutically acceptable salt thereof.

Abstract: Provided is a method of auto-adjusting the settings of a vehicle. The vehicle includes a first NFC device. The method includes: determining whether an electrical device is an authorized device through the first NFC device communicating with a second NFC device of the electrical device, the electrical device storing an identification information; obtaining a user's preference settings to the vehicle according to the identification information from the electrical device upon a condition that the electrical device is the authorized device; and adjusting the settings of the vehicle with the user's preference settings.

Abstract: A two-way up-down curtain includes a fixed top base including a device space and its bottom is drilled several eyelets. A coil rope control device is located in the device space is coiled with a first and a second thread. The threads penetrate through the eyelet in the bottom of the fixed top base. A curtain under the fixed top base includes a mobile top, a bottom and a curtain. The first thread penetrates through the mobile top, curtain and bottom downwards, and through the bottom downwards with an extended end. A pulling base is only fixed to the extended end of the first thread mutually, so that the user can push and pull the mobile top or the pulling base by hand to change the state of the curtain. The mobile top can be actually prevented from moving to result in clearance to the fixed top base.

Abstract: A two-way up-down curtain includes a fixed top base including a device space and its bottom is drilled several eyelets. A coil rope control device is located in the device space is coiled with a first and a second thread. The threads penetrate through the eyelet in the bottom of the fixed top base. A curtain under the fixed top base includes a mobile top, a bottom and a curtain. The first thread penetrates through the mobile top, curtain and bottom downwards, and through the bottom downwards with an extended end. A pulling base is only fixed to the extended end of the first thread mutually, so that the user can push and pull the mobile top or the pulling base by hand to change the state of the curtain. The mobile top can be actually prevented from movina to result in clearance to the fixed top base.

Abstract: A charger protection device (20) includes an oscillator (201), a resistor (204) electronically connected to the oscillator, a capacitor (203) electronically connected to the resistor and a switch (202). The oscillator (201), the resistor (204) and the capacitor (203) form an oscillating circuit. The switch is electronically connected to the capacitor, and a voltage across the capacitor is input to the switch.

Abstract: A charger protection device (20) includes an oscillator (201), a resistor (204) electronically connected to the oscillator, a capacitor (203) electronically connected to the resistor and a switch (202). The oscillator (201), the resistor (204) and the capacitor (203) form an oscillating circuit. The switch is electronically connected to the capacitor, and a voltage across the capacitor is input to the switch.

Abstract: The scalable planar DMOS transistor structure of the present invention comprises a scalable source region surrounded by a planar gate region. The scalable source region comprises a p-base diffusion region being formed in a n? epitaxial semiconductor layer through a ring-shaped implantation window, a n+ source diffusion ring being formed in a surface portion of the p-base diffusion region through the ring-shaped implantation window, a p+ contact diffusion region being formed in a middle semiconductor surface portion through a self-aligned implantation window being surrounded by the ring-shaped implantation window, and a self-aligned source contact window being formed on the p+ contact diffusion region and the n+ source diffusion ring surrounded by a sidewall dielectric spacer. The planar gate region comprises a patterned heavily-doped polycrystalline-silicon gate layer being formed on a gate dielectric layer and capped locally with or without metal silicide layers.

Abstract: The self-aligned Schottky-barrier clamped planar DMOS transistor structure comprises a self-aligned source region being surrounded by a planar gate region. The self-aligned source region comprises a moderately-doped p-base diffusion ring being formed in a lightly-doped N? epitaxial semiconductor layer, a heavily-doped n+ source diffusion ring being formed within the moderately-doped p-base diffusion ring, and a Schottky-barrier contact with the moderately-doped p-base diffusion ring acted as a diffusion guard ring being formed in a middle semiconductor surface portion of the self-aligned source region. The planar gate region comprises a patterned heavily-doped polycrystalline-silicon gate layer being silicided with or without metal silicide layers. The self-aligned source region further comprises a lightly-doped p? diffusion region being formed beneath a middle portion of the moderately-doped p-base diffusion ring.

Abstract: A multi-layer printed circuit board (PCB) includes a first wire layer, a middle layer above the first wire layer, a second wire layer above the middle layer, and a slanting via formed in the middle layer and the second wire layer. The manufacturing method includes the steps of providing a first wire layer and forming a first wiring on the first wire layer, forming a middle layer on the first wire layer, forming a second wire layer on the middle layer, forming a slanting via in the middle layer and the second wire layer wherein the direction of the slanting via is not orthogonal to the first and the second wire layers, forming a second wiring on the second wire layer by an etching method, and forming an electroplated layer in the via to connect the first wiring and the second wiring.

Abstract: The self-aligned Schottky-barrier clamped trench DMOS transistor structure of the present invention comprises a Schottky-barrier diode being formed in a middle semiconductor portion of a self-aligned source region. The self-aligned source region comprises a lightly-doped epitaxial semiconductor layer, a moderately-doped base diffusion ring being formed in a surface portion of the lightly-doped epitaxial semiconductor layer surrounded by a trench gate region, a heavily-doped source diffusion ring being formed in a side surface portion of the moderately-doped base diffusion ring, and a self-aligned source contact being formed on a semiconductor surface of the self-aligned source region surrounded by a sidewall dielectric spacer. The trench gate region comprises a self-aligned conductive gate layer being formed over a gate dielectric layer lined over a trenched semiconductor surface in a shallow trench with or without a thicker isolation dielectric layer being formed on a bottom surface of the shallow trench.

Abstract: A self-aligned trench DMOS transistor structure of the present invention comprises a self-aligned source structure and a self-aligned trench gate structure, in which the self-aligned source structure comprises a p-base diffusion region, a self-aligned n+ source diffusion ring, a self-aligned p+ contact diffusion region, and a self-aligned source contact window; the self-aligned trench gate structure comprises a self-aligned silicided conductive gate structure, a self-aligned polycided conductive gate structure or a self-aligned polycided trenched conductive gate structure. The self-aligned trench DMOS transistor structure as described is fabricated by using only one masking photoresist step and can be easily scaled down to obtain a high-density trench DMOS power transistor with ultra low on-resistance, low gate-interconnection parasitic resistance, and high device ruggedness.

Abstract: A labeling method for a printed circuit board comprising a first layout face and a second layout face opposite to the first layout face. The labeling method comprises defining a track region in the first layout face, defining a first mapping region mapped by the track region on the second layout face; and defining a first corresponding region on the second layout face completely enclosing the first mapping region.

Abstract: The self-aligned Schottky-barrier clamped planar DMOS transistor structure comprises a self-aligned source region being surrounded by a planar gate region. The self-aligned source region comprises a moderately-doped p-base diffusion ring being formed in a lightly-doped N? epitaxial semiconductor layer, a heavily-doped n+ source diffusion ring being formed within the moderately-doped p-base diffusion ring, and a Schottky-barrier contact with the moderately-doped p-base diffusion ring acted as a diffusion guard ring being formed in a middle semiconductor surface portion of the self-aligned source region. The planar gate region comprises a patterned heavily-doped polycrystalline-silicon gate layer being silicided with or without metal silicide layers. The self-aligned source region further comprises a lightly-doped p? diffusion region being formed beneath a middle portion of the moderately-doped p-base diffusion ring.

Abstract: The LOCOS-based junction-pinched Schottky rectifier comprises a raised diffusion guard ring surrounded by an outer LOCOS field oxide layer, a raised diffusion grid or a plurality of raised diffusion rings or stripes surrounded by the raised diffusion guard ring, a plurality of recessed semiconductor surfaces formed on a lightly-doped epitaxial semiconductor layer surrounded by the raised diffusion guard ring and the raised diffusion grid or by the raised diffusion guard ring and the plurality of raised diffusion rings or stripes, and a metal silicide layer or a metal layer being at least formed over a portion of the raised diffusion guard ring, the plurality of recessed semiconductor surfaces and the raised diffusion grid or the plurality of raised diffusion rings or stripes. A plurality of compensated diffusion layers can be formed in surface portions of the lightly-doped epitaxial semiconductor layer under the plurality of recessed semiconductor surfaces.

Abstract: The scalable planar DMOS transistor structure of the present invention comprises a scalable source region surrounded by a planar gate region. The scalable source region comprises a p-base diffusion region being formed in a n? epitaxial semiconductor layer through a ring-shaped implantation window, a n+ source diffusion ring being formed in a surface portion of the p-base diffusion region through the ring-shaped implantation window, a p+ contact diffusion region being formed in a middle semiconductor surface portion through a self-aligned implantation window being surrounded by the ring-shaped implantation window, and a self-aligned source contact window being formed on the p+ contact diffusion region and the n+ source diffusion ring surrounded by a sidewall dielectric spacer. The planar gate region comprises a patterned heavily-doped polycrystalline-silicon gate layer being formed on a gate dielectric layer and capped locally with or without metal silicide layers.