Abstract: The LOCOS-based Schottky barrier diode of the present invention comprises a raised diffusion guard ring surrounded by an outer LOCOS field oxide layer, a recessed semiconductor substrate with or without a compensated diffusion layer surrounded by the raised diffusion guard ring, a metal silicide layer formed over a portion of the raised diffusion guard ring and the recessed semiconductor substrate, and a patterned metal layer formed at least over the metal silicide layer, wherein the raised diffusion guard ring is formed between an inner LOCOS field oxide layer and the outer LOCOS field oxide layer and the recessed semiconductor substrate is formed by removing the inner LOCOS field oxide layer. The LOCOS-based Schottky barrier diode comprises the raised diffusion guard ring to reduce junction curvature effect on reverse breakdown voltage, the recessed semiconductor substrate to reduce forward voltage, and the compensated diffusion layer to reduce reverse leakage current.

Abstract: The self-aligned trench-type DMOS transistor structure comprises a self-aligned source region being surrounded by a trench gate region. The self-aligned source region comprises a moderately-doped p-base diffusion region formed in a lightly-doped epitaxial semiconductor substrate, a self-aligned heavily-doped n+ source diffusion ring formed in a side surface portion of the moderately-doped p-base diffusion region, a heavily-doped p+ contact diffusion region formed in a surface portion of the moderately-doped p-base diffusion region surrounded by the heavily-doped n+ source diffusion ring, and a self-aligned source contact window formed by a semiconductor surface surrounded by a sidewall dielectric spacer.

Abstract: A multi-layer printed circuit board (PCB) includes a first wire layer, a middle layer above the first wire layer, a second wire layer above the middle layer, and a slanting via formed in the middle layer and the second wire layer. The manufacturing method includes the steps of providing a first wire layer and forming a first wiring on the first wire layer, forming a middle layer on the first wire layer, forming a second wire layer on the middle layer, forming a slanting via in the middle layer and the second wire layer wherein the direction of the slanting via is not orthogonal to the first and the second wire layers, forming a second wiring on the second wire layer by an etching method, and forming an electroplated layer in the via to connect the first wiring and the second wiring.

Abstract: A LOCOS Schottky barrier contact structure of the present invention comprises a raised diffusion guard ring being surrounded by an outer LOCOS field oxide layer, a recessed semiconductor substrate being surrounded by the raised diffusion guard ring, a metal silicide layer being formed over the raised diffusion guard ring and the recessed semiconductor substrate, and a patterned metal layer being formed over a portion of the outer LOCOS field oxide layer and the metal silicide layer, wherein the raised diffusion guard ring is formed between an inner LOCOS field oxide layer and the outer LOCOS field oxide layer and the recessed semiconductor substrate is formed by removing the inner LOCOS field oxide layer. The LOCOS Schottky barrier contact structure offers the raised diffusion guard ring to eliminate junction curvature effect on reverse breakdown voltage and the outer LOCOS field oxide layer with a much better metal step coverage.

Abstract: A self-aligned trench DMOS transistor structure of the present invention comprises a self-aligned source structure and a self-aligned trench gate structure, in which the self-aligned source structure comprises a p-base diffusion region, a self-aligned n+ source diffusion ring, a self-aligned p+ contact diffusion region, and a self-aligned source contact window; the self-aligned trench gate structure comprises a self-aligned silicided conductive gate structure, a self-aligned polycided conductive gate structure or a self-aligned polycided trenched conductive gate structure. The self-aligned trench DMOS transistor structure as described is fabricated by using only one masking photoresist step and can be easily scaled down to obtain a high-density trench DMOS power transistor with ultra low on-resistance, low gate-interconnection parasitic resistance, and high device ruggedness.

Abstract: A self-aligned source structure is disclosed by the present invention, in which a p-body diffusion region is formed in an n? epitaxial silicon layer on an n+ silicon substrate through a patterned window; a p+ diffusion region is formed within the p-body diffusion region through a first self-aligned implantation window surrounded by a first sidewall dielectric spacer being formed over and on a silicon nitride layer; an n+ source diffusion ring is formed in a surface portion of the p-body diffusion region and on an extended portion of the p+ diffusion region through a second self-aligned implantation window formed between the silicon nitride layer and a masking layer surrounded by the first sidewall dielectric spacer; and a self-aligned source contact window is formed on the n+ source diffusion ring surrounded by a second sidewall dielectric spacer and on the p+ diffusion region surrounded by the n+ source diffusion ring.

Abstract: A self-aligned planar DMOS transistor structure is disclosed, in which a p-body diffusion region is selectively formed in an n?/n+ epitaxial silicon substrate; a self-aligned p+ contact diffusion region is formed within the p-body diffusion region through a first self-aligned implantation window surrounded by a first sacrificial dielectric spacer; a self-aligned n+ source diffusion ring is formed in a surface portion of the p-body diffusion region through a second self-aligned implantation window formed between a protection dielectric layer and a self-aligned implantation masking layer surrounded by the sacrificial dielectric spacer; a self-aligned source contact window is formed on the self-aligned n+ source diffusion ring surrounded by a sidewall dielectric spacer and on the self-aligned p+ contact diffusion region surrounded by the self-aligned n+ source diffusion ring; and a heavily-doped polycrystalline-silicon gate layer is selectively silicided in a self-aligned manner.

Abstract: The self-aligned floating-gate structure with a high coupling ratio being formed by one masking photoresist step is disclosed by the present invention, which comprises a first conductive layer over a tunneling-dielectric layer being formed over a semiconductor substrate in an active region and two extended second conductive layers being separately formed over etched-back field-oxide layers in nearby STI regions. Each of the extended second conductive layers is defined by a sidewall dielectric spacer being formed over each sidewall of the active region for forming a first-type self-aligned floating-gate structure and is formed by a sidewall conductive spacer being formed over each sidewall of the active region for forming a second-type self-aligned floating-gate structure, wherein thin sidewall conductive spacers are formed over sidewalls of the extended second conductive layers to alleviate the corner field-emission effects.

Abstract: A stack-gate flash cell structure of the present invention comprises a gate region being formed between common-source/drain regions. The common-source/drain region comprises a common-source/drain diffusion region, an etched-back planarized silicon dioxide layer being formed over a portion of a tunneling dielectric layer, and a pair of extended floating-gate spacers being formed over side portions of the etched-back planarized silicon dioxide layer. The gate region comprises a major floating-gate being integrated with nearby two extended floating-gate spacers to form an integrated floating-gate. A word line together with an intergate dielectric layer being at least formed over the integrated floating-gate are simultaneously patterned and etched. A cell isolation region is formed outside of the word line and between the common-source/drain regions. The stack-gate flash cell structure is used to implement two contactless flash memory arrays.

Abstract: A stack-gate flash cell structure of the present invention comprises a gate region being formed between common-source/drain regions. The common-source/drain region comprises a common-source/drain diffusion region, an etched-back planarized silicon dioxide layer being formed over a portion of a tunneling dielectric layer, and a pair of extended floating-gate spacers being formed over side portions of the etched-back planarized silicon dioxide layer. The gate region comprises a major floating-gate being integrated with nearby two extended floating-gate spacers to form an integrated floating-gate. A word line together with an intergate dielectric layer being at least formed over the integrated floating-gate are simultaneously patterned and etched. A cell isolation region is formed outside of the word line and between the common-source/drain regions. The stack-gate flash cell structure is used to implement two contactless flash memory arrays.

Abstract: The stack-gate flash memory cell structure of the present invention comprises a floating-gate structure with a thinner floating-gate layer being formed in a central portion by using a spacer-formation technique; an implanted region being formed in the central portion of a channel for adjusting threshold-voltage and forming a punch-through stop; and a highly conductive control-gate structure spaced with an intergate-dielectric layer being formed over the floating-gate structure. The contactless NOR-type array of the present invention comprises a plurality of common-source conductive bus lines and a plurality of planarized common-drain conductive islands being integrated with a plurality of metal bit-lines. The contactless parallel common-source/drain bit-line array comprises a plurality of common-source/drain conductive bit-lines and a plurality of metal word-lines being integrated with a plurality of planarized control-gate conductive islands.

Abstract: A stacked-gate cell structure having a tapered floating-gate layer and a laterally graded source/drain diffusion profile is implemented to form NAND cell strings over a self-aligned STI structure having a high coupling ratio. The paired string select lines and the paired ground select lines being formed over one-side tapered floating-gate layers are simultaneously defined by a spacer formation technique and are therefore scalable. Each of common-source conductive bus lines is formed over a first flat bed between a pair of sidewall dielectric spacers being formed over sidewalls of the paired ground select lines. A plurality of planarized common-drain conductive islands are formed over common-drain diffusion regions between another pair of sidewall dielectric spacers being formed over sidewalls of the paired string select lines and are patterned simultaneously with a plurality of metal bit-lines by using a masking photoresist step.

Abstract: A self-aligned trench-type DRAM structure comprising a self-aligned DRAM capacitor structure and a self-aligned DRAM transistor structure are disclosed by the present invention, in which the self-aligned DRAM capacitor structure comprises a deep-trench capacitor region and a shallow-trench-isolation region being defined by a spacer technique and the self-aligned DRAM transistor structure comprises a scalable gate-stack region and a common-drain region being defined by another spacer technique. The self-aligned trench-type DRAM structure is used to implement two contactless DRAM arrays. A first-type contactless DRAM array comprises a plurality of metal bit-lines integrated with planarized common-drain conductive islands and a plurality of highly conductive word-lines. A second-type contactless DRAM array comprises a plurality of metal word-lines integrated with planarized conductive-gate islands and a plurality of common-drain conductive bit-lines.

Abstract: A stack-gate non-volatile memory device with a tapered floating-gate structure is disclosed by the present invention, in which the tapered floating-gate structure offers a longer effective channel length to alleviate the punch-through effect and a larger surface area for erasing or programming between the tapered floating-gate structure and the integrated common-source/drain conductive structure. The stack-gate non-volatile memory devices of the present invention are implemented into three contactless array architectures: a contactless NOR-type array, a contacless NAND-type array, and a contactless parallel common-source/drain conductive bit-lines array. The features and advantages of the contactless memory arrays are a smaller cell size of 4F2, a smaller common-source/drain bus-line resistance and capacitance, a higher erasing speed, and a smaller bit/word-line resistance and capacitance, as compared to the prior arts.

Abstract: A scaled MOSFET device of the present invention comprises a shallow-trench-isolation structure being formed on a semiconductor substrate; a conductive-gate structure having a pair of second conductive sidewall spacers formed over each inner sidewall of a gate region and on a first conductive layer and first raised field-oxide layers for forming an implant region in a central portion of a channel and a planarized third conductive layer for forming a salicide-gate structure or a polycide-gate structure; a buffer-dielectric layer being formed over each sidewall of the conductive-gate structure for forming lightly-doped source/drain diffusion regions; a first sidewall dielectric spacer being formed over each sidewall of the buffer-dielectric layers for forming heavily-doped source/drain diffusion regions; and a second sidewall dielectric spacer being formed over each sidewall of the first sidewall dielectric spacers for forming a self-aligned silicidation contact over each of the heavily-doped source/drain diffus

Abstract: The stack-type DRAM memory structure of the present invention comprises a plurality of self-aligned thin third conductive islands over shallow heavily-doped source diffusion regions without dummy transistors to obtain a cell size of 6F2 or smaller; a rectangular tube-shaped cavity having a conductive island formed above a nearby transistor-stack being formed over each of the self-aligned thin third conductive islands to offer a larger surface area for forming a high-capacity DRAM capacitor of the present invention; a planarized third conductive island being formed between a pair of first sidewall dielectric spacers and on each of shallow heavily-doped common-drain diffusion regions to offer a larger contact area and a higher contact integrity; and a plurality of planarized conductive contact-islands being formed over the planarized third conductive islands to eliminate the aspect-ratio effect and being patterned and etched simultaneously with a plurality of bit lines.

Abstract: A self-aligned lateral-transistor DRAM cell structure is disclosed by the present invention, in which a trench structure comprises a trench region and a trench-isolation region being formed in a side portion of the trench region and a self-aligned lateral-transistor structure comprises a merged common-source diffusion region, a self-aligned gate-stack region, and a self-aligned common-drain diffusion region being formed in another side portion of the trench region by using spacer-formation techniques. The unit cell size of the self-aligned lateral-transistor DRAM cell structure can be fabricated to be equal to 6 F2 or smaller. The self-aligned lateral-transistor DRAM cell structure is used to implement two contactless DRAM arrays for high-speed read and write operations.

Abstract: A dual-bit floating-gate flash cell structure comprises a gate region being formed between a common-source region and a common-drain region. The gate region comprises a pair of floating-gates being defined by a pair of second sidewall dielectric spacers and a select-gate dielectric layer being formed between the pair of floating-gates. The common-source/drain region comprises a common-source/drain diffusion region or a pair of isolated source/drain diffusion regions being divided by a shallow trench isolation formed between a pair of first sidewall dielectric spacers. A word line being formed over an intergate dielectric layer is at least formed over the pair of floating-gates and the select-gate dielectric layer. Based on common-source/drain diffusion regions and isolated source/drain diffusion regions of the dual-bit floating-gate cell structure, two different contactless flash memory arrays are formed.

Abstract: A stacked-gate cell structure having a tapered floating-gate layer and a laterally graded source/drain diffusion profile is implemented to form NAND cell strings over a self-aligned STI structure having a high coupling ratio. The paired string select lines and the paired ground select lines being formed over one-side tapered floating-gate layers are simultaneously defined by a spacer formation technique and are therefore scalable. Each of common-source conductive bus lines is formed over a first flat bed between a pair of sidewall dielectric spacers being formed over sidewalls of the paired ground select lines. A plurality of planarized common-drain conductive islands are formed over common-drain diffusion regions between another pair of sidewall dielectric spacers being formed over sidewalls of the paired string select lines and are patterned simultaneously with a plurality of metal bit-lines by using a masking photoresist step.

Abstract: The self-aligned floating-gate structure with a high coupling ratio being formed by one masking photoresist step is disclosed by the present invention, which comprises a first conductive layer over a tunneling-dielectric layer being formed over a semiconductor substrate in an active region and two extended second conductive layers being separately formed over etched-back field-oxide layers in nearby STI regions. Each of the extended second conductive layers is defined by a sidewall dielectric spacer being formed over each sidewall of the active region for forming a first-type self-aligned floating-gate structure and is formed by a sidewall conductive spacer being formed over each sidewall of the active region for forming a second-type self-aligned floating-gate structure, wherein thin sidewall conductive spacers are formed over sidewalls of the extended second conductive layers to alleviate the corner field-emission effects.